NFC-enabled, tattoo-like stretchable biosensor manufactured by "cut-and-paste" method. - Hyoyoung Jeong; Taewoo Ha; Irene Kuang; Linxiao Shen; Zhaohe Dai; Nan Sun 001; Nanshu Lu (EMBC, 2017)

A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. - Yi Zhong; Shaolan Li; Arindam Sanyal; Xiyuan Tang; Linxiao Shen; Siliang Wu; Nan Sun 001 (A-SSCC, 2018)

A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor. - Linxiao Shen; Nanshu Lu; Nan Sun 001 (IEEE J. Solid State Circuits, 2018)

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. - Shaolan Li; Wenda Zhao; Biying Xu; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Nanshu Lu; David Z. Pan; Nan Sun 001 (CICC, 2019)

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. - Xiyuan Tang; Yi Shen 007; Linxiao Shen; Wenda Zhao; Zhangming Zhu; Visvesh Sathe 001; Nan Sun 001 (CICC, 2019)

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. - Biying Xu; Yibo Lin; Xiyuan Tang; Shaolan Li; Linxiao Shen; Nan Sun 001; David Z. Pan (DAC, 2019)

Device Layer-Aware Analytical Placement for Analog Circuits. - Biying Xu; Shaolan Li; Chak-Wa Pui; Derong Liu 002; Linxiao Shen; Yibo Lin; Nan Sun 001; David Z. Pan (ISPD, 2019)

A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. - Linxiao Shen; Yi Shen 007; Xiyuan Tang; Chen-Kai Hsu; Wei Shi 011; Shaolan Li; Wenda Zhao; Abhishek Mukherjee; Nan Sun 001 (ISSCC, 2019)

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. - Xiyuan Tang; Shaolan Li; Linxiao Shen; Wenda Zhao; Xiangxing Yang; Randy Williams; Jiaxin Liu; Zhichao Tan; Neal A. Hall; Nan Sun 001 (ISSCC, 2019)

A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. - Linxiao Shen; Abhishek Mukherjee; Shaolan Li; Xiyuan Tang; Nanshu Lu; Nan Sun 001 (VLSI Circuits, 2019)

An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. - Xiyuan Tang; Begum Kasap; Linxiao Shen; Xiangxing Yang; Wei Shi 011; Nan Sun 001 (VLSI Circuits, 2019)

A Two-Step ADC With a Continuous-Time SAR-Based First Stage. - Linxiao Shen; Nan Sun 001; Yi Shen 007; Zhelu Li; Wei Shi 011; Xiyuan Tang; Shaolan Li; Wenda Zhao; Mantian Zhang; Zhangming Zhu (IEEE J. Solid State Circuits, 2019)

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. - Mingjie Liu; Wuxi Li; Keren Zhu 001; Biying Xu; Yibo Lin; Linxiao Shen; Xiyuan Tang; Nan Sun 001; David Z. Pan (ASP-DAC, 2020)

A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. - Xin Xin 005; Linxiao Shen; Xiyuan Tang; Yi Shen 007; Jueping Cai; Nan Sun 001 (A-SSCC, 2020)

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. - Hanrui Wang 002; Kuan Wang; Jiacheng Yang; Linxiao Shen; Nan Sun 001; Hae-Seung Lee; Song Han 003 (DAC, 2020)

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. - Mingjie Liu; Keren Zhu 001; Jiaqi Gu 002; Linxiao Shen; Xiyuan Tang; Nan Sun 001; David Z. Pan (DATE, 2020)

16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation. - Jiaxin Liu; Xiyuan Tang; Wenda Zhao; Linxiao Shen; Nan Sun 001 (ISSCC, 2020)

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. - Xiyuan Tang; Xiangxing Yang; Wenda Zhao; Chen-Kai Hsu; Jiaxin Liu; Linxiao Shen; Abhishek Mukherjee; Wei Shi 011; David Z. Pan; Nan Sun 001 (ISSCC, 2020)

A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. - Zhelu Li; Arnab Dutta 004; Abhishek Mukherjee; Xiyuan Tang; Linxiao Shen; Lenian He; Nan Sun 001 (VLSI Circuits, 2020)

A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation. - Jiaxin Liu; Xiyuan Tang; Wenda Zhao; Linxiao Shen; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. - Yi Shen 007; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Xin Xin 005; Shubin Liu; Zhangming Zhu; Visvesh Sathe 001; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. - Xiyuan Tang; Shaolan Li; Xiangxing Yang; Linxiao Shen; Wenda Zhao; Randall P. Williams; Jiaxin Liu; Zhichao Tan; Neal A. Hall; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. - Xiyuan Tang; Linxiao Shen; Begum Kasap; Xiangxing Yang; Wei Shi 011; Abhishek Mukherjee; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. - Xiyuan Tang; Xiangxing Yang; Wenda Zhao; Chen-Kai Hsu; Jiaxin Liu; Linxiao Shen; Abhishek Mukherjee; Wei Shi 011; Shaolan Li; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. - Wenda Zhao; Shaolan Li; Biying Xu; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Nanshu Lu; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. - Yi Zhong; Shaolan Li; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Siliang Wu; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. - Linxiao Shen; Zijie Gao; Xiangxing Yang; Wei Shi 011; Nan Sun 001 (ISSCC, 2021)

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. - Wei Shi 011; Jiaxin Liu; Abhishek Mukherjee; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Nan Sun 001 (ISSCC, 2021)

Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. - Heyi Li; Zhichao Tan; Yuanxin Bao; Han Xiao 006; Hao Zhang 119; Kaixuan Du; Linxiao Shen; Jiayoon Ru; Yihan Zhang 002; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. - Abhishek Mukherjee; Miguel Gandara; Xiangxing Yang; Linxiao Shen; Xiyuan Tang; Chen-Kai Hsu; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network. - Zhixuan Wang; Ying Liu 069; Peng Zhou; Zhichao Tan; Haitao Fan; Yihan Zhang 002; Linxiao Shen; Jiayoon Ru; Yangyuan Wang; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. - Zhixuan Wang; Hao Zhang 119; Yihan Zhang 002; Linxiao Shen; Jiayoon Ru; Haitao Fan; Zhichao Tan; Yangyuan Wang; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems. - Le Ye; Zhixuan Wang; Ying Liu 069; Peiyu Chen; Heyi Li; Hao Zhang 119; Meng Wu 005; Wei He; Linxiao Shen; Yihan Zhang 002; Zhichao Tan; Yangyuan Wang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme. - Hao Zhang 119; Linxiao Shen; Shichuang Zhang; Heyi Li; Yihan Zhang 002; Zhichao Tan; Ru Huang 001; Le Ye (CICC, 2022)

A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique. - Xinhang Xu; Siyuan Ye; Jihang Gao; Yihan Zhang 002; Linxiao Shen; Le Ye (ISCAS, 2022)

An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu 069; Zhixuan Wang; Wei He; Linxiao Shen; Yihan Zhang 002; Peiyu Chen; Meng Wu 005; Hao Zhang 119; Peng Zhou; Jinguang Liu; Guangyu Sun 003; Jiayoon Ru; et al. (ISSCC, 2022)

Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. - Yihan Zhang 002; Chang Xue; Xiao Wang; Tianyi Liu; Jihang Gao; Peiyu Chen; Jinguang Liu; Linan Sun; Linxiao Shen; Jiayoon Ru; Le Ye; Ru Huang 001 (ISSCC, 2022)

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. - Xiyuan Tang; Jiaxin Liu; Yi Shen 007; Shaolan Li; Linxiao Shen; Arindam Sanyal; Kareem Ragab; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology. - Xinhang Xu; Linxiao Shen; Siyuan Ye; Jiayi Wu; Zhuoyi Chen; Jihang Gao; Jiajia Cui; Yihan Zhang 002; Ru Huang 001; Le Ye (ESSCIRC, 2023)

An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications. - Yiqi Jing; Zhixuan Wang; Linxiao Shen; Yihan Zhang 002; Peiyu Chen; Jiayoon Ru; Le Ye (ISCAS, 2023)

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. - Peiyu Chen; Meng Wu 005; Wentao Zhao; Jiajia Cui; Zhixuan Wang; Yadong Zhang; Qijun Wang; Jiayoon Ru; Linxiao Shen; Tianyu Jia; Yufei Ma 002; Le Ye; et al. (ISSCC, 2023)

A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. - Jihang Gao; Linxiao Shen; Heyi Li; Siyuan Ye; Jie Li; Xinhang Xu; Jiajia Cui; Yunhung Gao; Ru Huang 001; Le Ye (ISSCC, 2023)

A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control. - Yihan Zhang 002; You You; Wenjie Ren; Xinhang Xu; Linxiao Shen; Jiayoon Ru; Ru Huang 001; Le Ye (ISSCC, 2023)

A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. - Xin Xin 005; Linxiao Shen; Xiyuan Tang; Yi Shen 007; Jueping Cai; Xingyuan Tong; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu 069; Yufei Ma 002; Wei He; Zhixuan Wang; Linxiao Shen; Jiayoon Ru; Ru Huang 001; Le Ye (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Interactive Analog Layout Editing With Instant Placement and Routing Legalization. - Xiaohan Gao; Haoyi Zhang; Mingjie Liu; Linxiao Shen; David Z. Pan; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Research progress on low-power artificial intelligence of things (AIoT) chip design. - Le Ye; Zhixuan Wang; Tianyu Jia; Yufei Ma 002; Linxiao Shen; Yihan Zhang 002; Heyi Li; Peiyu Chen; Meng Wu 005; Ying Liu 069; Yiqi Jing; Hao Zhang 119; et al. (Sci. China Inf. Sci., 2023)

An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input. - Jie Li; Linxiao Shen; Siyuan Ye; Jihang Gao; Jiajia Cui; Xinhang Xu; Zhuoyi Chen; Yaohui Luan; Yuanxin Bao; Ru Huang 001; Le Ye (CICC, 2024)

Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network. - Ao Shi; Yizhou Zhang; Lixia Han; Zheng Zhou; Yiyang Chen; Lifeng Liu; Linxiao Shen; Peng Huang 004; Xiaoyan Liu; Jinfeng Kang (ISCAS, 2024)

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique. - Zhuoyi Chen; Linxiao Shen; Siyuan Ye; Jihang Gao; Jie Li; Jiajia Cui; Xinhang Xu; Yaohui Luan; Hao Zhang 119; Le Ye; Ru Huang 001 (ISSCC, 2024)

3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS. - Xinhang Xu; Siyuan Ye; Yaohui Luan; Jihang Gao; Jie Li; Jiajia Cui; Hao Zhang 119; Ru Huang 001; Linxiao Shen; Le Ye (ISSCC, 2024)

9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting. - Siyuan Ye; Linxiao Shen; Jihang Gao; Jie Li; Zhuoyi Chen; Xinhang Xu; Jiajia Cui; Hao Zhang 119; Xing Zhang 002; Le Ye; Ru Huang 001 (ISSCC, 2024)

Post-layout simulation driven analog circuit sizing. - Xiaohan Gao; Haoyi Zhang; Siyuan Ye; Mingjie Liu; David Z. Pan; Linxiao Shen; Runsheng Wang; Yibo Lin; Ru Huang 001 (Sci. China Inf. Sci., 2024)

A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC. - Heyi Li; Kaixuan Du; Yuanxin Bao; Yanchi Dong; Jiayoon Ru; Han Xiao 006; Hao Zhang 119; Zhixuan Wang; Yi Zhong; Linxiao Shen; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2024)

A Single-Ended SAR ADC With Fully Differential DAC Switching Scheme for IoT Applications. - Kaixuan Du; Maoqiang Liu; Zhixuan Wang; Heyi Li; Yuanxin Bao; Linxiao Shen; Le Ye (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks. - Ao Shi; Yizhou Zhang; Lixia Han; Zheng Zhou; Yiyang Chen; Haozhang Yang; Lifeng Liu; Linxiao Shen; Xiaoyan Liu; Jinfeng Kang; Peng Huang 004 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 110µW 99.5dB-SNDR 20kHz-BW Intrinsically Linear CTDSM with Hybrid Gm-Boosting OTA and Tri-Level FIR DACs. - Xinhang Xu; Yaohui Luan; Jie Li; Jihang Gao; Kwok Cheong Li; Jiajia Cui; Ru Huang 001; Linxiao Shen (CICC, 2025)

An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration. - Zhuoyi Chen; Siyuan Ye; Jihang Gao; Jie Li; Jiajia Cui; Xinhang Xu; Yaohui Luan; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

18.3: A 93.3dB SNDR, 180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch-Error-Shaping Technique and Negative-R-Assisted Residue Integrator. - Jihang Gao; Yaohui Luan; Siyuan Ye; Xinhang Xu; Zhuoyi Chen; Jiajia Cui; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction. - Ying Liu 069; Jie Li; Qining Zhang; Tianhao Zhao; Chenhao Shi; Ninghui Shang; Peiyu Chen; Xiaohuan Ge; Yufei Ma 002; Linxiao Shen; Zhixuan Wang; Ru Huang 001; et al. (ISSCC, 2025)

18.2 A 12.2μW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD ΔΣM with Gain-Embedded Bootstrapped Sampler. - Yaohui Luan; Xinhang Xu; Jihang Gao; Jiajia Cui; Zhuoyi Chen; Siyuan Ye; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting. - Siyuan Ye; Jiajia Cui; Jihang Gao; Jie Li; Xing Zhang 002; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

6.6 A 320×256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-Paralleled Light-Driven 20b Current-to-Phase ADC. - Yi Zhuo; Hangyu Lu; Ding Ma; Zheng Zhou; Linxiao Shen; Yacong Zhang; Zhongjian Chen; Xixin Cao; Yimao Cai; Ning Li; Wengao Lu (ISSCC, 2025)

An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS. - Jihang Gao; Siyuan Ye; Jie Li; Xinhang Xu; Zhuoyi Chen; Jiajia Cui; Yaohui Luan; Ru Huang 001; Le Ye; Linxiao Shen (IEEE J. Solid State Circuits, 2025)

A Flying-Capacitor-Based Reset Scheme for Low Power Dynamic Comparator. - Kwok Cheong Li; Xinhang Xu; Jihang Gao; Siyuan Ye; Jiajia Cui; Yacong Zhang; Ru Huang 001; Linxiao Shen (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting. - Siyuan Ye; Jihang Gao; Jie Li; Zhuoyi Chen; Xinhang Xu; Jiajia Cui; Yaohui Luan; Le Ye; Xing Zhang 002; Ru Huang 001; Linxiao Shen (IEEE J. Solid State Circuits, 2025)

A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing. - Peiyu Chen; Wentao Zhao; Meng Wu 005; Linxiao Shen; Tianyu Jia; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE J. Solid State Circuits, 2025)