Developments in computer simulation of gate level physical logic. - Lionel Bening (DAC, 1979)

Developments in logic network path delay analysis. - Lionel Bening; Thomas A. Lane; Curtis R. Alexander; James E. Smith 001 (DAC, 1982)

Critical path issue in VLSI design. - Habib Youssef; Eugene Shragowitz; Lionel Bening (ICCAD, 1989)

A Two-State Methodology for RTL Logic Simulation. - Lionel Bening (DAC, 1999)

Principles of verifiable RTL design - a functional coding style supporting verification processes in Verilog. - Lionel Bening; Harry Foster (Kluwer, 2001)

Optimizing Multiple EDA Tools within the ASIC Design Flow. - Lionel Bening; Harry Foster (IEEE Des. Test Comput., 2001)