VHDL-AMS modeling of a multi-standard phase locked loop. - Benjamin Nicolle; Lionel Geynet; Emeric de Foucauld; William Tatinian; Gilles Jacquemod (ICECS, 2005)

Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology. - Gilles Jacquemod; Lionel Geynet; Benjamin Nicolle; Emeric de Foucauld; William Tatinian; Pierre Vincent (Microelectron. J., 2008)