Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. - Liqiong Wei; Zhanping Chen; Mark Johnson; Kaushik Roy 001; Vivek De (DAC, 1998)

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. - Zhanping Chen; Mark Johnson; Liqiong Wei; Kaushik Roy 001 (ISLPED, 1998)

Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. - Liqiong Wei; Zhanping Chen; Kaushik Roy 001; Yibin Ye; Vivek De (DAC, 1999)

Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. - Kaushik Roy 001; Liqiong Wei; Zhanping Chen (ISCAS (1), 1999)

Design and optimization of dual-threshold circuits for low-voltage low-power applications. - Liqiong Wei; Zhanping Chen; Kaushik Roy 001; Mark C. Johnson; Yibin Ye; Vivek De (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Power minimization by simultaneous dual-Vth assignment and gate-sizing. - Liqiong Wei; Kaushik Roy 001; Cheng-Kok Koh (CICC, 2000)

High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. - Naran Sirisantana; Liqiong Wei; Kaushik Roy 001 (ICCD, 2000)

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. - Zhanping Chen; Liqiong Wei; Kaushik Roy 001 (ISQED, 2000)

Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. - Liqiong Wei; Kaushik Roy 001; Vivek De (VLSI Design, 2000)

On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. - Zhanping Chen; Liqiong Wei; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. - Tanay Karnik; Yibin Ye; James W. Tschanz; Liqiong Wei; Steven M. Burns; Venkatesh Govindarajulu; Vivek De; Shekhar Borkar (DAC, 2002)

IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. - Zhanping Chen; Liqiong Wei; Ali Keshavarzi; Kaushik Roy 001 (IEEE Des. Test Comput., 2002)

Vertically integrated SOI circuits for low-power and high-performance applications. - Liqiong Wei; Rongtian Zhang; Kaushik Roy 001; Zhanping Chen; David B. Janes (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; Ian Post; et al. (ISSCC, 2007)

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; et al. (IEEE J. Solid State Circuits, 2008)

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (ISSCC, 2009)

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (IEEE J. Solid State Circuits, 2010)

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. - Fatih Hamzaoglu; Yih Wang; Pramod Kolar; Liqiong Wei; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE Des. Test Comput., 2011)

A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. - Kyung-Hoae Koo; Liqiong Wei; John Keane 001; Uddalak Bhattacharya; Eric A. Karl; Kevin Zhang 001 (VLSIC, 2015)

A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V. - Pulkit Jain; Umut Arslan; Meenakshi Sekhar; Blake C. Lin; Liqiong Wei; Tanaya Sahu; Juan Alzate-vinasco; Ajay Vangapaty; Mesut Meterelliyoz; Nathan Strutt; Albert B. Chen; Patrick Hentges; et al. (ISSCC, 2019)

A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique. - Liqiong Wei; Juan G. Alzate; Umut Arslan; Justin Brockman; Nilanjan Das; Kevin Fischer; Tahir Ghani; Oleg Golonzka; Patrick Hentges; Rawshan Jahan; Pulkit Jain; Blake C. Lin; et al. (ISSCC, 2019)