High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA. - Lirida A. B. Naviner; Jean-Luc Danger; C. Laurent (FPGA, 1999)

Antialiasing filtering influences on ADC specifications for radio receivers. - Elizabeth Colin; Patrick Loumeau; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2001)

Design and implementation of cascade decimation filter for radio communications. - Khaled Grati; Adel Ghazel; Lirida A. B. Naviner; Faker Moatamri (ICECS, 2001)

Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers. - Elizabeth Colin; Lirida A. B. Naviner; Patrick Loumeau; Jean-François Naviner (VTC Fall, 2001)

Relaxed decimation filter specifications for wireless transceivers. - Khaled Grati; Adel Ghazel; Lirida A. B. Naviner (ICECS, 2002)

Analog to digital conversion: technical aspects. - Patrick Loumeau; Jean-François Naviner; Hervé Petit; Lirida A. B. Naviner; Patricia Desgreys (Ann. des Télécommunications, 2002)

On design and implementation of a decimation filter for multistandard wireless transceivers. - Adel Ghazel; Lirida A. B. Naviner; Khaled Grati (IEEE Trans. Wirel. Commun., 2002)

On baseband considerations for multistandard RF receivers. - Elizabeth Colin; Lirida Alves de Barros Naviner (ICECS, 2003)

Hardware implementation issues of a BMS decoding approach for AG based codes. - Zouhair M. Belkoura; Lirida A. B. Naviner (WCNC, 2003)

A finger configuration algorithm for a reconfigurable Rake receiver. - Ioannis Krikidis; Jean-Luc Danger; Lirida A. B. Naviner (WCNC, 2004)

Design and hardware implementation of digital channel selection decimating filter for multistandard receiver. - Khaled Grati; Adel Ghazel; Lirida A. B. Naviner (ICECS, 2005)

Heterogeneous implementation of a rake receiver for DS-CDMA communication systems. - Daniel C. de Souza; Ioannis Krikidis; Lirida A. B. Naviner; Jean-Luc Danger; M. A. de Barros; B. G. A. Neto (ICECS, 2005)

Reconfigurable Implementation Issues of a Detection Scheme for DS-CDMA High Data Rate Connections. - Ioannis Krikidis; Jean-Luc Danger; Lirida A. B. Naviner (PIMRC, 2005)

Yield and reliability issues in nanoelectronic technologies. - Denis Teixeira Franco; Jean-François Naviner; Lirida A. B. Naviner (Ann. des Télécommunications, 2006)

An iterative reconfigurability approach for WCDMA high-data-rate communications. - Ioannis Krikidis; Jean-Luc Danger; Lirida A. B. Naviner (IEEE Wirel. Commun., 2006)

Methods and Metrics for Reliability Assessment. - Lirida Alves de Barros Naviner; Jean-François Naviner; Denis Teixeira Franco; Maí Correia R. de Vasconcelos (Fault-Tolerant Distributed Algorithms on VLSI Chips, 2008)

Reliability analysis of logic circuits based on signal probability. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2008)

On the output events in concurrent error detection schemes. - Maí Correia R. de Vasconcelos; Denis Teixeira Franco; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2008)

Signal probability for reliability evaluation of logic circuits. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2008)

Relevant metrics for evaluation of concurrent error detection schemes. - Maí Correia R. de Vasconcelos; Denis Teixeira Franco; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2008)

A 65 nm CMOS Digital Processor for Multi-mode Time Interleaved High-pass SigmaDelta A/D Converters. - Ali Beydoun; Van Tam Nguyen 001; Lirida A. B. Naviner; Patrick Loumeau (ISCAS, 2009)

Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. - Josep Torras Flaquer; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (ICECS, 2010)

Level matrix propagation for reliability analysis of nano-scale circuits based on probabilistic transfer matrix. - Hicham Ezzat; Lirida A. B. Naviner (ISQED, 2010)

On evaluating the signal reliability of self-checking arithmetic circuits. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (SBCCI, 2010)

Fast reliability analysis of combinatorial logic circuits using conditional probabilities. - Josep Torras Flaquer; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (Microelectron. Reliab., 2010)

An efficient tool for reliability improvement based on TMR. - Elaine Crespo Marques; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2010)

Using error tolerance of target application for efficient reliability improvement of digital circuits. - G. G. dos Santos; Elaine Crespo Marques; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2010)

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. - Josep Torras Flaquer; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (IOLTS, 2011)

Progressive module redundancy for fault-tolerant designs in nanoelectronics. - Tian Ban; Lirida A. B. Naviner (Microelectron. Reliab., 2011)

FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level. - Lirida A. B. Naviner; Jean-François Naviner; G. G. dos Santos Jr.; Elaine Crespo Marques; Nilson M. Paiva Jr. (Microelectron. Reliab., 2011)

Green solutions for future LTE PMR networks. - Xavier Pons Masbernat; Christophe Gruet; Frédéric Fraysse; Serge Contal; Lirida A. B. Naviner (CAMAD, 2012)

Transient fault analysis of CORDIC processor. - Ting An; Matteo Causo; Lirida Alves de Barros Naviner; Philippe Matherat (ICECS, 2012)

Parallel scaling-free and area-time efficient CORDIC algorithm. - Matteo Causo; Ting An; Lirida Alves de Barros Naviner (ICECS, 2012)

A new fault-tolerant architecture for CLBs in SRAM-based FPGAs. - Arwa Ben Dhia; Lirida Alves de Barros Naviner; Philippe Matherat (ICECS, 2012)

Automatic selective hardening against soft errors: A cost-based and regularity-aware approach. - Samuel N. Pagliarini; Arwa Ben Dhia; Lirida Alves de Barros Naviner; Jean-François Naviner (ICECS, 2012)

Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster. - Arwa Ben Dhia; Lirida A. B. Naviner; Philippe Matherat (IOLTS, 2012)

Selective hardening methodology for combinational logic. - Samuel Nascimento Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (LATW, 2012)

Majority voter: Signal probability, reliability and error bound characteristics. - Tian Ban; Lirida Alves de Barros Naviner (MWSCAS, 2012)

Reliability analysis of a Reed-Solomon decoder. - Kaikai Liu; Tian Ban; Lirida A. B. Naviner; Jean-François Naviner (MWSCAS, 2012)

Exploring the feasibility of selective hardening for combinational logic. - Samuel N. Pagliarini; G. G. dos Santos; Lirida Alves de Barros Naviner; Jean-François Naviner (Microelectron. Reliab., 2012)

Uplink energy efficiency in LTE systems. - Xavier Pons Masbernat; Raúl Palacios; Christophe Gruet; Lirida A. B. Naviner; Hugo Marques; Fabrizio Granelli; Jonathan Rodriguez 001 (CAMAD, 2013)

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. - Sébastien Sarrazin; Samuel Evain; Lirida Alves de Barros Naviner; Yannick Bonhomme; Valentin Gherman (DATE, 2013)

A low cost reliable architecture for S-Boxes in AES processors. - Ting An; Lirida Alves de Barros Naviner; Philippe Matherat (DFTS, 2013)

Evaluating CLB designs under multiple SETs in SRAM-based FPGAs. - Arwa Ben Dhia; Lirida A. B. Naviner; Philippe Matherat (DFTS, 2013)

Reliability analysis of combinational circuits with the influences of noise and single-event transients. - Kaikai Liu; Hao Cai 001; Ting An; Lirida A. B. Naviner; Jean-François Naviner; Hervé Petit (DFTS, 2013)

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology. - Kaikai Liu; Ting An; Hao Cai 001; Lirida A. B. Naviner; Jean-François Naviner; Hervé Petit (EUROCON, 2013)

A defect-tolerant cluster in a mesh SRAM-based FPGA. - Arwa Ben Dhia; Saif-Ur Rehman; Adrien Blanchardon; Lirida A. B. Naviner; Mounir Benabdenbi; Roselyne Chotin-Avot; Emna Amouri; Habib Mehrez; Zied Marrakchi (FPT, 2013)

Single event transient mitigation through pulse quenching: Effectiveness at circuit level. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2013)

Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs. - Arwa Ben Dhia; Lirida A. B. Naviner; Philippe Matherat (LATW, 2013)

Modeling of transient faults and fault-tolerant design in nanoelectronics. - Tian Ban; Jianxin Wang 002; Ting An; Lirida A. B. Naviner (MWSCAS, 2013)

Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis. - Samuel N. Pagliarini; Tian Ban; Lirida A. B. Naviner; Jean-François Naviner (MWSCAS, 2013)

Evaluation of fault-tolerant composite field AES S-boxes under multiple transient faults. - Ting An; Lirida Alves de Barros Naviner; Philippe Matherat (NEWCAS, 2013)

Selective hardening against multiple faults employing a net-based reliability analysis. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (NEWCAS, 2013)

A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. - Arwa Ben Dhia; Samuel N. Pagliarini; Lirida Alves de Barros Naviner; Habib Mehrez; Philippe Matherat (Microelectron. Reliab., 2013)

SNaP: A novel hybrid method for circuit reliability assessment under multiple faults. - Samuel N. Pagliarini; Arwa Ben Dhia; Lirida Alves de Barros Naviner; Jean-François Naviner (Microelectron. Reliab., 2013)

Battery-aware network discovery algorithm for mobile terminals within heterogeneous networks. - Xavier Pons Masbernat; Saud Althunibat; Godfrey Kibalya; Christophe Gruet; Lirida A. B. Naviner; Fabrizio Granelli (CAMAD, 2014)

Shadow-scan design with low latency overhead and in-situ slack-time monitoring. - Sébastien Sarrazin; Samuel Evain; Ivan Miro Panades; Alexandre Valentian; Suresh Pajaniradja; Lirida Alves de Barros Naviner; Valentin Gherman (ETS, 2014)

An energy efficient vertical handover decision algorithm. - Xavier Pons Masbernat; Agapi Mesodiakaki; Christophe Gruet; Lirida A. B. Naviner; Ferran Adelantado; Luis Alonso 001; Christos V. Verikoukis (GLOBECOM Workshops, 2014)

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. - Lirida A. B. Naviner; Kaikai Liu; Hao Cai 001; Jean-François Naviner (ICICDT, 2014)

Cross logic: A new approach for defect-tolerant circuits. - Mariem Slimani; Arwa Ben Dhia; Lirida A. B. Naviner (ICICDT, 2014)

Comparative study of defect-tolerant multiplexers for FPGAs. - Arwa Ben Dhia; Mariem Slimani; Lirida A. B. Naviner (IOLTS, 2014)

A hybrid reliability assessment method and its support of sequential logic modelling. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner; Dhiraj K. Pradhan (IOLTS, 2014)

Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. - Sébastien Sarrazin; Samuel Evain; Ivan Miro Panades; Lirida Alves de Barros Naviner; Valentin Gherman (IOLTS, 2014)

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. - Saif-Ur Rehman; Adrien Blanchardon; Arwa Ben Dhia; Mounir Benabdenbi; Roselyne Chotin-Avot; Lirida A. B. Naviner; Lorena Anghel; Habib Mehrez; Emna Amouri; Zied Marrakchi (ISVLSI, 2014)

Improving the robustness of a switch box in a mesh of clusters FPGA. - Arwa Ben Dhia; Mariem Slimani; Lirida A. B. Naviner (LATW, 2014)

Simulation study of aging in CMOS binary adders. - Ting An; Hao Cai 001; Lirida Alves de Barros Naviner (MIPRO, 2014)

Analytical method for reliability assessment of concurrent checking circuits under multiple faults. - Ting An; Kaikai Liu; Lirida Alves de Barros Naviner (MIPRO, 2014)

Efficient implementation for accurate analysis of CED circuits against multiple faults. - Ting An; Kaikai Liu; Hao Cai 001; Lirida Alves de Barros Naviner (MIXDES, 2014)

Reliability-aware delay faults evaluation of CMOS flip-flops. - Hao Cai 001; Kaikai Liu; Lirida Alves de Barros Naviner (MIXDES, 2014)

A defect-tolerant multiplexer using differential logic for FPGAs. - Arwa Ben Dhia; Mariem Slimani; Lirida A. B. Naviner (MIXDES, 2014)

Analytical methods to assess transient faults effects in logic circuits. - Lirida Alves de Barros Naviner (MWSCAS, 2014)

OxRAM-based non volatile flip-flop in 28nm FDSOI. - Nenad Jovanovic; Olivier Thomas; Elisa Vianello; Jean-Michel Portal; Bosko Nikolic; Lirida A. B. Naviner (NEWCAS, 2014)

Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses. - You Wang 002; Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Lirida A. B. Naviner; Weisheng Zhao (Microelectron. Reliab., 2014)

A tool for transient fault analysis in combinational circuits. - Mariem Slimani; Lirida A. B. Naviner (ICECS, 2015)

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. - Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Gilles Gasiot; Fady Abouzeid; Sylvain Clerc; Lirida A. B. Naviner; Philippe Roche (IRPS, 2015)

An energy efficient D2D LTE structure for PMR based on FlashLinQ. - Xavier Pons; Christophe Gruet; Eric Georgeaux; Lirida A. B. Naviner (ISWCS, 2015)

Partial triplication of a SPARC-V8 microprocessor using fault injection. - Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (LASCAS, 2015)

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction. - Lirida Alves de Barros Naviner; Hao Cai 001; You Wang 002; Weisheng Zhao; Arwa Ben Dhia (NEWCAS, 2015)

D2D broadcast communications for 4G PMR networks. - Xavier Pons Masbernat; Christophe Gruet; Eric Georgeaux; Lirida A. B. Naviner (NTMS, 2015)

Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method. - Ting An; Kaikai Liu; Hao Cai 001; Lirida A. B. Naviner (Microelectron. Reliab., 2015)

Cross-layer investigation of continuous-time sigma-delta modulator under aging effects. - Hao Cai 001; You Wang 002; Kaikai Liu; Lirida Alves de Barros Naviner; Hervé Petit; Jean-François Naviner (Microelectron. Reliab., 2015)

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; W. S. Zhao (Microelectron. Reliab., 2015)

A dual-rail compact defect-tolerant multiplexer. - Arwa Ben Dhia; Mariem Slimani; Hao Cai 001; Lirida A. B. Naviner (Microelectron. Reliab., 2015)

A novel analytical method for defect tolerance assessment. - Mariem Slimani; Arwa Ben Dhia; Lirida A. B. Naviner (Microelectron. Reliab., 2015)

Compact thermal modeling of spin transfer torque magnetic tunnel junction. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Yue Zhang 010; Jacques-Olivier Klein; Weisheng Zhao (Microelectron. Reliab., 2015)

Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation. - Fábio B. Armelin; Lírida A. B. Naviner; Roberto d'Amore; Irany A. Azevedo (ICECS, 2016)

Design considerations for reliable OxRAM-based non-volatile flip-flops in 28nm FD-SOI technology. - Nenad Jovanovic; Olivier Thomas; Elisa Vianello; Bosko Nikolic; Lirida A. B. Naviner (ISCAS, 2016)

Approximate computing in MOS/spintronic non-volatile full-adder. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Zhaohao Wang; Weisheng Zhao (NANOARCH, 2016)

A novel circuit design of true random number generator using magnetic tunnel junction. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Jacques-Olivier Klein; Jianlei Yang 001; Weisheng Zhao (NANOARCH, 2016)

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. - Francisco Veirano; Lirida A. B. Naviner; Fernando Silveira (PATMOS, 2016)

Inserting permanent fault input dependence on PTM to improve robustness evaluation. - Rafael B. Schivittz; Rafael Fritz; Denis Teixeira Franco; Lirida A. B. Naviner; Cristina Meinhardt; Paulo F. Butzen (SBCCI, 2016)

Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS. - Francisco Veirano; Fernando Silveira; Lirida A. B. Naviner (J. Low Power Electron., 2016)

Efficient reliability evaluation methodologies for combinational circuits. - Hao Cai 001; Kaikai Liu; Lirida Alves de Barros Naviner; You Wang 002; Mariem Slimani; Jean-François Naviner (Microelectron. Reliab., 2016)

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters. - Mariem Slimani; Paulo F. Butzen; Lirida A. B. Naviner; You Wang 002; Hao Cai 001 (Microelectron. Reliab., 2016)

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Xiaoxuan Zhao; Yue Zhang 010; Mariem Slimani; Jacques-Olivier Klein; Weisheng Zhao (Microelectron. Reliab., 2016)

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Wang Kang 001; Weisheng Zhao (ACM Great Lakes Symposium on VLSI, 2017)

Sparsity analysis using a mixed approach with greedy and LS algorithms on channel estimation. - Nilson Maciel de Paiva; Elaine Crespo Marques; Lirida Alves de Barros Naviner (ICFSP, 2017)

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Weisheng Zhao (ISVLSI, 2017)

Asymmetrical length biasing for energy efficient digital circuits. - Francisco Veirano; Fernando Silveira; Lirida A. B. Naviner (LASCAS, 2017)

Analysis of ageing effects on ARTIX7 XILINX FPGA. - Mariem Slimani; K. Benkalaia; Lirida A. B. Naviner (Microelectron. Reliab., 2017)

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits. - Francisco Veirano; Lirida A. B. Naviner; Fernando Silveira (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. - Menglin Han; Hao Cai 001; Jun Yang 006; Lirida A. B. Naviner; You Wang 002; Weisheng Zhao (APCCAS, 2018)

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. - Hao Cai 001; Menglin Han; You Wang 002; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (DCIS, 2018)

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning. - You Wang 002; Yue Zhang 010; Youguang Zhang; Weisheng Zhao; Hao Cai 001; Lirida A. B. Naviner (ACM Great Lakes Symposium on VLSI, 2018)

Compressed Sensing for Wideband HF Channel Estimation. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (ICFSP, 2018)

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Weiwei Shan; Jun Yang 006; Weisheng Zhao (ISCAS, 2018)

MRAM-on-FDSOI Integration: A Bit-Cell Perspective. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (ISVLSI, 2018)

Reliability evaluation of circuits designed in multi- and single-stage versions. - Rafael B. Schvittz; Matheus F. Pontes; Cristina Meinhardt; Denis Teixeira Franco; Lirida A. B. Naviner; Leomar S. da Rosa; Paulo F. Butzen (LASCAS, 2018)

Using FPGA self-produced transients to emulate SETs for SER estimation. - Fábio B. Armelin; Lírida A. B. Naviner; Roberto d'Amore (LATS, 2018)

Probability aware fault-injection approach for SER estimation. - Fábio B. Armelin; Lirida A. B. Naviner; Roberto d'Amore (LATS, 2018)

Design, Synthesis and Application of A Novel Approximate Adder. - Tian Ban; Baokun Wang; Lirida A. B. Naviner (MWSCAS, 2018)

Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology. - Nilson Maciel; Elaine Crespo Marques; Lirida A. B. Naviner; Hao Cai 001 (Microelectron. Reliab., 2018)

Deep Learning Approaches for Sparse Recovery in Compressive Sensing. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (ISPA, 2019)

Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM. - Mingyue Liu; Hao Cai 001; Menglin Han; Lei Xie; Jun Yang 006; Lirida A. B. Naviner (NANOARCH, 2019)

Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (SiPS, 2019)

A Review of Sparse Recovery Algorithms. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (IEEE Access, 2019)

Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI. - Francisco Veirano; Lirida A. B. Naviner; Fernando Silveira (Integr., 2019)

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Xinning Liu; Weiwei Shan; Jun Yang 006; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Magnetic Tunnel Junction-based Analog-to-Digital Converter using Spin Orbit Torque Mechanism. - Nilson Maciel; Elaine Crespo Marques; Lírida A. B. Naviner; Hao Cai 001 (ICECS, 2020)

Quad-Approx CNNs for Embedded Object Detection Systems. - Xuecan Yang; Sumanta Chaudhuri; Lirida A. B. Naviner; Laurence Likforman (ICECS, 2020)

Magnetic Tunnel Junction Applications. - Nilson Maciel; Elaine Crespo Marques; Lirida A. B. Naviner; Yongliang Zhou; Hao Cai 001 (Sensors, 2020)

Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM. - You-You Zhang; Lirida A. B. Naviner; Hao Cai 001 (ASICON, 2021)

Cryogenic In-MRAM Computing. - Yaoru Hou; We Ge; Yanan Guo 004; Lirida A. B. Naviner; You Wang 002; Bo Liu 019; Jun Yang 006; Hao Cai 001 (NANOARCH, 2021)

Hybrid MTJ-CMOS Integration for Sigma-Delta ADC. - Yu-ang Wu; Lirida A. B. Naviner; Hao Cai 001 (NANOARCH, 2021)

A survey of in-spin transfer torque MRAM computing. - Hao Cai 001; Bo Liu 019; Juntong Chen; Lirida A. B. Naviner; Yongliang Zhou; Zhen Wang 019; Jun Yang 006 (Sci. China Inf. Sci., 2021)

Minconvnets: a New Class of Multiplication-Less Neural Networks. - Xuecan Yang; Sumanta Chaudhuri; Laurence Likforman; Lirida A. B. Naviner (ICIP, 2022)

OPCoSA: an Optimized Product Code for space applications. - David C. C. Freitas; Jarbas Silveira; César A. M. Marcon; Lirida A. B. Naviner; João Cesar M. Mota (Integr., 2022)

Writing-only in-MRAM computing paradigm for ultra-low power applications. - Bo Liu 019; Mingyue Liu; Yongliang Zhou; Xiaofeng Hong; Hao Cai 001; Lirida Alves de Barros Naviner (Microprocess. Microsystems, 2022)

Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. - Esther Goudet; Luis Peña Treviño; Lirida A. B. Naviner; Jean-Marc Daveau; Philippe Roche (LATS, 2023)

Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms. - Hao Cai 001; Yaoru Hou; Mengdi Zhang; Bo Liu 019; Lirida Alves de Barros Naviner (IEEE Des. Test, 2023)

nMatrix: A New Decoding Algorithm for the Matrix ECC. - David C. C. Freitas; Lirida Alves de Barros Naviner; João Cesar Moura Mota; Jarbas Silveira; César A. M. Marcon; David Freitas Moura Mota; Alexandre Coelho (LADC, 2024)

Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using gem5. - Muhammad Awais; Maria Mushtaq; Lirida Naviner; Florent Bruguier; Jawad Haj-Yahya; Pascal Benoit (RSP, 2024)

Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching. - Zhenghan Fang; Lirida Naviner; Wen Wang; Wei Le; Hao Cai 001 (SBCCI, 2024)

Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning. - Esther Goudet; Luis Peña Treviño; Gutemberg G. dos Santos Júnior; Sayah El Hajji; Fabio Sureau; Lirida Naviner; Jean-Marc Daveau; Philippe Roche (SBCCI, 2024)

Check-Bit Region Exploration in Two-Dimensional Error Correction Codes. - David C. C. Freitas; David F. M. Mota; David Coelho; Humberto Fontinele; Alexandre Coelho; Jarbas Silveira; Lirida Naviner; João Mota; César A. M. Marcon (IEEE Access, 2024)

Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach. - Esther Goudet; Fabio Sureau; Paul Breuil; Luis Peña Treviño; Lirida A. B. Naviner; Jean-Marc Daveau; Philippe Roche (J. Electron. Test., 2024)

HYGENE: A Diffusion-Based Hypergraph Generation Method. - Dorian Gailhard; Enzo Tartaglione; Lirida Naviner; Jhony H. Giraldo (AAAI, 2025)

Approximate Analytical Model Evaluating Digital Systems Compliance with Automotive Standards. - Esther Goudet; Fabio Sureau; Manan Kaila; Rémi Germe; Luis Peña Treviño; Jean-Marc Daveau; Lirida Naviner; Philippe Roche (LATS, 2025)

Feature-aware Hypergraph Generation via Next-Scale Prediction. - Dorian Gailhard; Enzo Tartaglione; Lirida Naviner; Jhony H. Giraldo (CoRR, 2025)

A quality-configurable approximate cache design based on NAND-like SOT MRAM with high energy efficiency. - Zhengyi Hou; Luyao Shi; Yan Qiao; Bi Wang 002; Bi Wu; Lirida Naviner; Zhaohao Wang (Integr., 2026)