An integrated system for rapid prototyping of high performance algorithm specific data paths. - D. C. Chen; Lisa M. Guerra; E. H. Ng; Miodrag Potkonjak; D. P. Schultz; Jan M. Rabaey (ASAP, 1992)

Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations. - Miodrag Potkonjak; Lisa M. Guerra; Jan M. Rabaey (ASAP, 1993)

High Level Synthesis Techniques for Efficient Built-In-Self Repair. - Lisa M. Guerra; Miodrag Potkonjak; Jan M. Rabaey (DFT, 1993)

Instruction set mapping for performance optimization. - Miguel R. Corazao; Marwan A. Khalaf; Lisa M. Guerra; Miodrag Potkonjak; Jan M. Rabaey (ICCAD, 1993)

High level synthesis for reconfigurable datapath structures. - Lisa M. Guerra; Miodrag Potkonjak; Jan M. Rabaey (ICCAD, 1993)

Logic Optimization with Multi-Output Gates. - Yosinori Watanabe; Lisa M. Guerra; Robert K. Brayton (ICCD, 1993)

Concurrency characteristics in DSP programs. - Lisa M. Guerra; Miodrag Potkonjak; Jan M. Rabaey (ICASSP (2), 1994)

Design guidance in the power dimension. - Jan M. Rabaey; Lisa M. Guerra; Renu Mehra (ICASSP, 1995)

Performance optimization using template mapping for datapath-intensive high-level synthesis. - Miguel R. Corazao; Marwan A. Khalaf; Lisa M. Guerra; Miodrag Potkonjak; Jan M. Rabaey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Permissible functions for multioutput components in combinational logic optimization. - Yosinori Watanabe; Lisa M. Guerra; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Low-power architectural synthesis and the impact of exploiting locality. - Renu Mehra; Lisa M. Guerra; Jan M. Rabaey (J. VLSI Signal Process., 1996)

A partitioning scheme for optimizing interconnect power. - Renu Mehra; Lisa M. Guerra; Jan M. Rabaey (IEEE J. Solid State Circuits, 1997)

A Methodology for Guided Behavioral-Level Optimization. - Lisa M. Guerra; Miodrag Potkonjak; Jan M. Rabaey (DAC, 1998)

Functional debugging of systems-on-chip. - Darko Kirovski; Miodrag Potkonjak; Lisa M. Guerra (ICCAD, 1998)

Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's. - Lisa M. Guerra; Miodrag Potkonjak; Jan M. Rabaey (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification. - Lisa M. Guerra; Joachim Fitzner; Dipankar Talukdar; Chris Schläger; Bassam Tabbara; Vojin Zivojnovic (DAC, 1999)

Throughput optimization of general non-linear computations. - Inki Hong; Miodrag Potkonjak; Lisa M. Guerra (ICCAD, 1999)

Improving the observability and controllability of datapaths foremulation-based debugging. - Darko Kirovski; Miodrag Potkonjak; Lisa M. Guerra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Cut-based functional debugging for programmable systems-on-chip. - Darko Kirovski; Miodrag Potkonjak; Lisa M. Guerra (IEEE Trans. Very Large Scale Integr. Syst., 2000)