Mixed-signal circuits for embedded machine-learning applications. - Boris Murmann; Daniel Bankman; Elaina Chai; Daisuke Miyashita; Lita Yang (ACSSC, 2015)

SRAM voltage scaling for energy-efficient convolutional neural networks. - Lita Yang; Boris Murmann (ISQED, 2017)

Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks. - Lita Yang; Boris Murmann (ISVLSI, 2017)

BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS. - Bert Moons; Daniel Bankman; Lita Yang; Boris Murmann; Marian Verhelst (CICC, 2018)

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs. - Gage Hills; Daniel Bankman; Bert Moons; Lita Yang; Jake Hillard; Alex Kahng; Rebecca Park; Marian Verhelst; Boris Murmann; Max M. Shulaker; H.-S. Philip Wong; Subhasish Mitra (DAC, 2018)

Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor. - Lita Yang; Daniel Bankman; Bert Moons; Marian Verhelst; Boris Murmann (ISCAS, 2018)

An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS. - Daniel Bankman; Lita Yang; Bert Moons; Marian Verhelst; Boris Murmann (ISSCC, 2018)

An Always-On 3.8 $ mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS. - Daniel Bankman; Lita Yang; Bert Moons; Marian Verhelst; Boris Murmann (IEEE J. Solid State Circuits, 2019)

Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point. - Bita Darvish Rouhani; Daniel Lo; Ritchie Zhao; Ming Liu; Jeremy Fowers; Kalin Ovtcharov; Anna Vinogradsky; Sarah Massengill; Lita Yang; Ray Bittner; Alessandro Forin; Haishan Zhu; et al. (NeurIPS, 2020)

Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications. - Lita Yang; Robert M. Radway; Yu-Hsin Chen; Tony F. Wu; Huichu Liu; Elnaz Ansari; Vikas Chandra; Subhasish Mitra; Edith Beigné (IEEE Micro, 2022)

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. - Tony F. Wu; Huichu Liu; Huseyin Ekin Sumbul; Lita Yang; Dipti Baheti; Jeremy Coriell; William Koven; Anu Krishnan; Mohit Mittal; Matheus Trevisan Moreira; Max Waugaman; Laurent Ye; et al. (ISSCC, 2024)

Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices. - Lita Yang; Changjung Kao; Sriseshan Srikanth; Huseyin Ekin Sumbul; Tony F. Wu; Huichu Liu; Edith Beigné (MEMSYS, 2024)

A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint. - Huseyin Ekin Sumbul; Arne Symons; Lita Yang; Huichu Liu; Tony F. Wu; Matheus Trevisan Moreira; Debabrata Mohapatra; Abhinav Agarwal; Kaushik Ravindran; Chris Thompson; Yuecheng Li; Edith Beigné (DATE, 2025)