Bulk compensated CMOS squaring circuits. - Pak Kwong Chan; L. S. Ng; Liter Siek; M. S. Tse; J. Y. Ong; K. S. Lok (ISCAS (2), 1999)

A low-offset class-AB CMOS operational amplifier. - Pak K. Chan; Liter Siek; Hwee C. Tay; Jing H. Su (ISCAS, 2000)

A 0.18-µm 10-GHz CMOS ring oscillator for optical transceivers. - Hai Qi Liu; Wang Ling Goh; Liter Siek (ISCAS (2), 2005)

A new 4.3 ppm/°C voltage reference using standard CMOS process with 1V supply voltage. - Q. X. Zhang; Liter Siek (ISCAS (5), 2005)

1.8-V 10-GHZ ring VCO design using 0.18-μm CMOS technology. - Hai Qi Liu; Wang Ling Goh; Liter Siek (SoCC, 2005)

A two-step dynamic reference A/D converter. - Danping Li; Liter Siek (ECCTD, 2007)

A spur-reduction technique in a fully integrated CMOS frequency synthesizer for 5-GHz WLAN SOC. - Yuan Sun; Liter Siek (SoCC, 2007)

A Compact Current Mode Neuron Circuit with Gaussian Taper Learning Capability. - Fei Li; Chip-Hong Chang; Liter Siek (ISCAS, 2009)

A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning. - Hai Qi Liu; Wang Ling Goh; Liter Siek; Wei Meng Lim; Yue Ping Zhang (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A high speed tracking quantizer for Continuous-Time multi-bit sigma delta modulators. - Yoon Hwee Leow; Liter Siek (APCCAS, 2010)

A simplified approach for baseband recovery in SDR architectures. - Richard Wee Tar Ng; Liter Siek (APCCAS, 2010)

Analog-to-Digital Converter with energy recovery capability using adiabatic technique. - Howard Tang; Liter Siek (APCCAS, 2010)

A fully digital green LDO regulator dedicated for biomedical implant using a power-aware binary switching technique. - Chiang Liang Kok; Qi Huang; Di Zhu 003; Liter Siek; Wei Meng Lim (APCCAS, 2012)

A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. - Howard Tang; Joshua Yung Lih Low; Jeremy Yung Shern Low; Liter Siek; Ching-Chuen Jong; Chip-Hong Chang (APCCAS, 2012)

An ultra-compact green bio-regulator dedicated for brain cortical implant using a dynamic PSR enhancement technique. - Chiang Liang Kok; Liter Siek; Fei Gao 010; Yuanjin Zheng; Wei Meng Lim (EMBC, 2012)

A novel analog-to-residue conversion scheme based on clock overlapping technique. - Qi Huang; Di Zhu 003; Liter Siek (ISCAS, 2012)

A novel analog-to-residue converter for biomedical DSP application. - Di Zhu 003; Qi Huang; Zhao Chuan Lee; Yuanjin Zheng; Liter Siek (ISOCC, 2012)

A Novel Ultra-Low Power Two-Terminal Zener voltage Reference. - Chiang Liang Kok; Liter Siek; Wei Meng Lim (J. Circuits Syst. Comput., 2012)

Analysis and design of high performance frequency-interleaved ADC. - Lei Qiu 002; Yuanjin Zheng; Liter Siek (ISCAS, 2013)

A 400nW single-inductor dual-input-tri-output DC-DC buck-boost converter with maximum power point tracking for indoor photovoltaic energy harvesting. - Kin Wai Roy Chew; Zhuochao Sun; Howard Tang; Liter Siek (ISSCC, 2013)

A statistic based time skew calibration method for time-interleaved ADCs. - Lei Qiu 002; Yuanjin Zheng; Di Zhu 003; Liter Siek (ISCAS, 2014)

A Fixed-frequency hysteretic controlled buck DC-DC converter with improved load regulation. - Zhuochao Sun; Liter Siek; Ravinder Pal Singh; Minkyu Je (ISCAS, 2014)

Triple boundary multiphase with predictive interleaving technique for switched capacitor DC-DC converter regulation. - Zhekai Xiao; Chiang Liang Kok; Liter Siek (ISIC, 2014)

High accuracy time-mode duty-cycle-modulation-based temperature sensor for energy efficient system applications. - Di Zhu 003; Jiacheng Wang 001; Liter Siek; Chiang Liang Kok; Lei Qiu 002; Yuanjin Zheng (ISIC, 2014)

A 0.7 V low-power fully programmable Gaussian function generator for brain-inspired Gaussian correlation associative memory. - Fei Li; Chip-Hong Chang; Arindam Basu; Liter Siek (Neurocomputing, 2014)

A 1.33 µW 8.02-ENOB 100 kS/s Successive Approximation ADC With Supply Reduction Technique for Implantable Retinal Prosthesis. - Howard Tang; Zhuochao Sun; Kin Wai Roy Chew; Liter Siek (IEEE Trans. Biomed. Circuits Syst., 2014)

A 0.42-V Input Boost dc-dc Converter With Pseudo-Digital Pulsewidth Modulation. - Zhuochao Sun; Kin Wai Roy Chew; Howard Tang; Guolei Yu; Liter Siek (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device. - Howard Tang; Zhuochao Sun; Kin Wai Roy Chew; Liter Siek (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A low TC, supply independent and process compensated current reference. - Chundong Wu; Wang Ling Goh; Chiang Liang Kok; Wanlan Yang; Liter Siek (CICC, 2015)

Design of WPT coils to minimize AC resistance and capacitor stress applied to SS-topology. - Robin Tanzania; Fook Hoong Choo; Liter Siek (IECON, 2015)

A switched capacitor deadtime controller for DC-DC buck converter. - Chiang Liang Kok; Xin Li; Liter Siek; Di Zhu 003; Junjie Kong (ISCAS, 2015)

A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology. - Junjie Kong; Liter Siek; Chiang Liang Kok (ISCAS, 2015)

A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit. - Arjun Ramaswami Palaniappan; Dominic Maurath; Felix Kalathiparambil; Liter Siek (ISCAS, 2015)

A digital time skew calibration technique for time-interleaved ADCs. - Lei Qiu 002; Kai Tang 002; Yuanjin Zheng; Liter Siek (ISCAS, 2015)

A high efficiency rectifier for inductively power transfer application. - Qiong Wei Low; Liter Siek; Mi Zhou (VLSI-SoC, 2015)

A New Time-Mode On-Chip Oscillator-Based High Linearity and Low Power Temperature Sensor. - Di Zhu 003; Liter Siek (J. Circuits Syst. Comput., 2015)

A 400 nW Single-Inductor Dual-Input-Tri-Output DC-DC Buck-Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting. - Guolei Yu; Kin Wai Roy Chew; Zhuochao Sun; Howard Tang; Liter Siek (IEEE J. Solid State Circuits, 2015)

An Area-Efficient Current-Mode Bandgap Reference With Intrinsic Robust Start-Up Behavior. - Chengyue Yu; Liter Siek (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. - Junjie Kong; Stephan Henzler; Doris Schmitt-Landsiedel; Liter Siek (APCCAS, 2016)

A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration. - Lei Qiu 002; Kai Tang 002; Yan Zhu 001; Liter Siek; Yuanjin Zheng; Seng-Pan U (A-SSCC, 2016)

A close-loop time-mode temperature sensor with inaccuracy of -0.6°C/0.5°C from -40°C to 120°C. - Di Zhu 003; Jiacheng Wang 001; Liter Siek (ISCAS, 2016)

Digitally-controlled H-bridge DC-DC converter for micropower PV energy harvesting system. - Anh Khoa Bui; Zhekai Xiao; Liter Siek (ISIC, 2016)

A dual redundancy radiation-hardened Flip-Flop based on C-element in 65nm process. - Gibran Limi Jaya; Shoushun Chen; Liter Siek (ISIC, 2016)

Performance analysis on active rectifier structures for inductively powered application. - Qiong Wei Low; Mi Zhou; Liter Siek (ISIC, 2016)

Electronically tunable MOSFET-based resistor used in a variable gain amplifier or filter. - W. L. Tan; C. H. Chang; Liter Siek (ISIC, 2016)

Review of pulse generators for gated ring oscillator based Time-to-Digital converters. - Jian Sen Teh; Arjun Ramaswami Palaniappan; Liter Siek; Yuanjin Zheng (ISIC, 2016)

A switched-capacitor DC-DC converter with embedded fast NMOS-LDOs achieving low noise, low output voltage ripple and fast response. - Zhekai Xiao; Anh Khoa Bui; Liter Siek (ISIC, 2016)

A continuous switching mode step-down switched-capacitor regulator with inrush current control scheme. - Chengyue Yu; Xiang Zhang 007; Liter Siek (ISIC, 2016)

A high efficiency synchronous buck converter with adaptive dead-time control. - Mi Zhou; Qiong Wei Low; Liter Siek (ISIC, 2016)

Multichannel Time Skew Calibration for Time-Interleaved ADCs Using Clock Signal. - Lei Qiu 002; Yuanjin Zheng; Liter Siek (Circuits Syst. Signal Process., 2016)

A Filter Bank Mismatch Calibration Technique for Frequency-Interleaved ADCs. - Lei Qiu 002; Yuanjin Zheng; Liter Siek (Circuits Syst. Signal Process., 2016)

High-Accuracy Time-Mode Duty-Cycle-Modulation-Based Temperature Sensor for Energy-Efficient System Applications. - Di Zhu 003; Liter Siek; Yuanjin Zheng (Circuits Syst. Signal Process., 2016)

A 1 V 103 dB 3rd-Order Audio Continuous-Time ΔΣ ADC With Enhanced Noise Shaping in 65 nm CMOS. - Yoon Hwee Leow; Howard Tang; Zhuochao Sun; Liter Siek (IEEE J. Solid State Circuits, 2016)

A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs. - Lei Qiu 002; Kai Tang 002; Yuanjin Zheng; Liter Siek (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Asymmetrical Dead-Time Control Driver for Buck Regulator. - Chundong Wu; Wang Ling Goh; Chiang Liang Kok; Liter Siek; Yat-Hei Lam; Xi Zhu; Ravinder Pal Singh (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 0.9-V input PWM DCM boost converter with low output ripples and fast load transient response based on a novel square-root voltage mode (SRVM) control approach. - Hao Luo; Liter Siek (ISCAS, 2017)

A transient-enhanced low dropout regulator with rail to rail dynamic impedance attenuation buffer suitable for commercial design. - Kan Li 003; Yuanjin Zheng; Liter Siek (Microelectron. J., 2017)

A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission. - Xiaoyin Bai; Zhi-Hui Kong; Liter Siek (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Hysteretic Switched-Capacitor DC-DC Converter With Optimal Output Ripple and Fast Transient Response. - Zhekai Xiao; Anh Khoa Bui; Liter Siek (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An 80.4% Peak Power Efficiency Adaptive Supply Class H Power Amplifier for Audio Applications. - Xiang Zhang 007; Liter Siek (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Novel Edge Comparator with Input Time Hysteresis for Improved Edges Arbitration. - Jian Sen Teh; Liter Siek (ISCAS, 2018)

A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. - Jian Sen Teh; Liter Siek; Abdel Martinez Alonso; Anugerah Firdauzi; Akira Matsuzawa (ISCAS, 2018)

A Fast Transient Response DC-DC Converter with an Active Compensation Capacitor Module. - Mi Zhou; Zhuochao Sun; Zhekai Xiao; Qiong Wei Low; Liter Siek (ISCAS, 2018)

A 0.0186 mm2, 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants. - Arjun Ramaswami Palaniappan; Liter Siek (NORCAS, 2018)

An 87% Peak Efficiency, 37W, Class H Audio Amplifier with GaN Output Stage. - Nardi Utomo; Liter Siek; Heng Goh Yap; Don Disney; Lawrence Selvaraj; Lulu Peng (NORCAS, 2018)

A 0.058 mm2, 24µW Temperature Sensor in 40nm CMOS Process with ± 0.5, °C Inaccuracy from -55 to 175°C. - Di Zhu 003; Liter Siek (Circuits Syst. Signal Process., 2018)

A Single-Stage Direct-Conversion AC-DC Converter for Inductively Powered Application. - Qiong Wei Low; Mi Zhou; Liter Siek (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS. - Lei Qiu 002; Kai Tang 002; Yuanjin Zheng; Liter Siek; Yan Zhu 001; Seng-Pan U (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS. - Arjun Ramaswami Palaniappan; Liter Siek (ISCAS, 2019)

A TDC-less all-digital phase locked loop for medical implant applications. - Arjun Ramaswami Palaniappan; Liter Siek (Microprocess. Microsystems, 2019)

A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications. - Devrishi Khanna; Chirn Chye Boon; Pilsoon Choi; Liter Siek; Bei Liu; Chenyang Li 008 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Single-Stage Dual-Output Tri-Mode AC-DC Regulator for Inductively Powered Application. - Qiong Wei Low; Liter Siek (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Multiloop Control for Fast Transient DC-DC Converter. - Mi Zhou; Zhuochao Sun; Qiong Wei Low; Liter Siek (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS. - Oscar Morales Chacon; J. Jacob Wikner; Atila Alvandpour; Liter Siek (NorCAS, 2020)

Deep Neural Network (DNN) Optimized Design of 2.45 GHz CMOS Rectifier With 73.6% Peak Efficiency for RF Energy Harvesting. - Wendy Wee Yee Lau; Heng Wah Ho; Liter Siek (IEEE Trans. Circuits Syst., 2020)

A RF-DC Rectifier with Dual Voltage Polarity Self-Biasing for Wireless Sensor Node Application. - Teo Boon Chiat Terence; Venkadasamy Navaneethan; Lim Xian Yang; Nardi Utomo; Ziming Liu; Tan Chong Boon; Seah Yun Da Bryan; Ji-Jon Sit; Liter Siek (ISCAS, 2021)

Low Voltage Low Power Output Programmable OCL-LDO with Embedded Voltage Reference. - Nardi Utomo; Boon Chiat Terence Teo; Xian Yang Lim; Venkadasamy Navaneethan; Ziming Liu; Chong Boon Tan; Yun Da Bryan Seah; Ying Hung Yvonne Lam; Liter Siek (ISCAS, 2021)

A digital switching scheme to reduce DAC glitches using code-dependent randomization. - Oscar Morales Chacon; J. Jacob Wikner; Atila Alvandpour; Liter Siek (NorCAS, 2021)

A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique. - Ao Zhou 003; Xin Ding 003; Chirn Chye Boon; Liter Siek; Yuan Liang 004; Yangtao Dong (IEEE Access, 2021)

Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters. - Oscar Morales Chacon; J. Jacob Wikner; Atila Alvandpour; Liter Siek (MIXDES, 2022)

An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS. - Gibran Limi Jaya; Chirn Chye Boon; Shoushun Chen; Liter Siek (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Battery-input Hysteretic Buck Converter with 430nA Quiescent Current and 5×104 Load Current Dynamic Range for Wearable Biomedical Devices. - Ziming Liu; Wang Ling Goh; Liter Siek; Yuan Gao 011 (BioCAS, 2023)

A Review on Current-Steering DAC Design. - Xian Yang Lim; Wu Cong Lim; Boon Chiat Terence Teo; Venkadasamy Navaneethan; Chong Boon Tan; Nardi Utomo; Liter Siek; Atila Alvandpour (ICEIC, 2023)

Performance Analysis of Self-biasing Technique for Differential RF-DC Rectifier in IoT Application. - Boon Chiat Terence Teo; Wu Cong Lim; Xian Yang Lim; Venkadasamy Navaneethan; Chong Boon Tan; Nardi Utomo; Liter Siek (ICEIC, 2023)

An 85.1% Peak Efficiency, Low Power Class H Audio Amplifier With Full Class H Operation. - Nardi Utomo; Boon Chiat Terence Teo; Xian Yang Lim; Venkadasamy Navaneethan; Ziming Liu; Chong Boon Tan; Liter Siek (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Comparative Analysis of Passive, Active, and Hybrid Cell Balancing for Optimal Battery Performance. - Wu Cong Lim; Boon Chiat Terence Teo; Xian Yang Lim; Liter Siek; Eng Leong Tan (ICEIC, 2024)

Recent Development of High-PCE CMOS RF-DC Rectifier With Wide PIN Dynamic Range: Strategies and Trends - Review. - Boon Chiat Terence Teo; Wu Cong Lim; Xian Yang Lim; Venkadasamy Navaneethan; Liter Siek (IEEE Access, 2024)

Adaptive Active Balancing in Battery Management Systems with Comprehensive System Modeling. - Wu Cong Lim; Boon Chiat Terence Teo; Xian Yang Lim; Liter Siek; Eng Leong Tan (ICEIC, 2025)