Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. - Peng Gu; Shuangchen Li; Dylan C. Stow; Russell Barnes; Liu Liu 017; Yuan Xie 001; Eren Kursun (ACM Great Lakes Symposium on VLSI, 2016)

NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory. - Shuangchen Li; Liu Liu 017; Peng Gu; Cong Xu 002; Yuan Xie 001 (ICCAD, 2016)

CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis. - Maohua Zhu; Liu Liu 017; Chao Wang 003; Yuan Xie 001 (CoRR, 2016)

Building energy-efficient multi-level cell STT-RAM caches with data compression. - Liu Liu 017; Ping Chi; Shuangchen Li; Yuanqing Cheng; Yuan Xie 001 (ASP-DAC, 2017)

PIRT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Applications on Heterogeneous Architectures. - Liu Liu 017; Shaoshan Liu; Zhe Zhang 006; Bo Yu 014; Jie Tang 003; Yuan Xie 001 (CoRR, 2018)

L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks. - Shuang Wu; Guoqi Li; Lei Deng 003; Liu Liu 017; Yuan Xie 001; Luping Shi (CoRR, 2018)

Dynamic Sparse Graph for Efficient Deep Learning. - Liu Liu 017; Lei Deng 003; Xing Hu 001; Maohua Zhu; Guoqi Li; Yufei Ding 001; Yuan Xie 001 (ICLR (Poster), 2019)

L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks. - Shuang Wu; Guoqi Li; Lei Deng 003; Liu Liu 017; Dong Wu; Yuan Xie 001; Luping Shi (IEEE Trans. Neural Networks Learn. Syst., 2019)

INVITED: Computation on Sparse Neural Networks and its Implications for Future Hardware. - Fei Sun; Minghai Qin; Tianyun Zhang; Liu Liu 017; Yen-Kuang Chen; Yuan Xie 001 (DAC, 2020)

Boosting Deep Neural Network Efficiency with Dual-Module Inference. - Liu Liu 017; Lei Deng 003; Zhaodong Chen; Yuke Wang; Shuangchen Li; Jingwei Zhang; Yihua Yang; Zhenyu Gu; Yufei Ding 001; Yuan Xie 001 (ICML, 2020)

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture. - Liu Liu 017; Zheng Qu; Lei Deng 003; Fengbin Tu; Shuangchen Li; Xing Hu 001; Zhenyu Gu; Yufei Ding 001; Yuan Xie 001 (MICRO, 2020)

Computation on Sparse Neural Networks: an Inspiration for Future Hardware. - Fei Sun; Minghai Qin; Tianyun Zhang; Liu Liu 017; Yen-Kuang Chen; Yuan Xie 001 (CoRR, 2020)

SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars. - Lei Deng 003; Yuan Xie 001; Ling Liang; Guanrui Wang; Liang Chang 002; Xing Hu 001; Xin Ma; Liu Liu 017; Jing Pei; Guoqi Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

ENMC: Extreme Near-Memory Classification via Approximate Screening. - Liu Liu 017; Jilan Lin; Zheng Qu; Yufei Ding 001; Yuan Xie 001 (MICRO, 2021)

Efficient tensor core-based GPU kernels for structured sparsity under reduced precision. - Zhaodong Chen; Zheng Qu; Liu Liu 017; Yufei Ding 001; Yuan Xie 001 (SC, 2021)

Π-RT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Vision Applications on Heterogeneous Architectures. - Liu Liu 017; Jie Tang 003; Shaoshan Liu; Bo Yu 014; Yuan Xie 001; Jean-Luc Gaudiot (Computer, 2021)

Transformer Acceleration with Dynamic Sparse Attention. - Liu Liu 017; Zheng Qu; Zhaodong Chen; Yufei Ding 001; Yuan Xie 001 (CoRR, 2021)

DOTA: detect and omit weak attentions for scalable transformer acceleration. - Zheng Qu; Liu Liu 017; Fengbin Tu; Zhaodong Chen; Yufei Ding 001; Yuan Xie 001 (ASPLOS, 2022)

A one-for-all and o(v log(v ))-cost solution for parallel merge style operations on sorted key-value arrays. - Bangyan Wang; Lei Deng 003; Fei Sun; Guohao Dai; Liu Liu 017; Yu Wang 002; Yuan Xie 001 (ASPLOS, 2022)

INSPIRE: in-storage private information retrieval via protocol and architecture co-design. - Jilan Lin; Ling Liang; Zheng Qu; Ishtiyaque Ahmad; Liu Liu 017; Fengbin Tu; Trinabh Gupta; Yufei Ding 001; Yuan Xie 001 (ISCA, 2022)

A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Ling Liang; Liu Liu 017; Yufei Ding 001; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (ISSCC, 2022)

Enabling Data Movement and Computation Pipelining in Deep Learning Compiler. - Guyue Huang; Yang Bai; Liu Liu 017; Yuke Wang; Bei Yu 001; Yufei Ding 001; Yuan Xie 001 (CoRR, 2022)

Dynamic Sparse Attention for Scalable Transformer Acceleration. - Liu Liu 017; Zheng Qu; Zhaodong Chen; Fengbin Tu; Yufei Ding 001; Yuan Xie 001 (IEEE Trans. Computers, 2022)

Elastic Processing and Hardware Architectures for Machine Learning - Liu Liu 017 (2022)

ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification. - Siqi Li; Fengbin Tu; Liu Liu 017; Jilan Lin; Zheng Wang 075; Yangwook Kang; Yufei Ding 001; Yuan Xie 001 (ISCA, 2023)

ALCOP: Automatic Load-Compute Pipelining in Deep Learning Compiler for AI-GPUs. - Guyue Huang; Yang Bai; Liu Liu 017; Yuke Wang; Bei Yu 001; Yufei Ding 001; Yuan Xie 001 (MLSys, 2023)

Dynamic N: M Fine-Grained Structured Sparse Attention Mechanism. - Zhaodong Chen; Zheng Qu; Yuying Quan; Liu Liu 017; Yufei Ding 001; Yuan Xie 001 (PPoPP, 2023)

TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Ling Liang; Liu Liu 017; Yufei Ding 001; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

SmartQuant: CXL-Based AI Model Store in Support of Runtime Configurable Weight Quantization. - Rui Xie 006; Asad Ul Haq; Linsen Ma; Krystal Sun; Sanchari Sen; Swagath Venkataramani; Liu Liu 017; Tong Zhang 002 (IEEE Comput. Archit. Lett., 2024)

Reimagining Memory Access for LLM Inference: Compression-Aware Memory Controller Design. - Rui Xie 006; Asad Ul Haq; Linsen Ma; Yunhua Fang; Zirak Burzin Engineer; Liu Liu 017; Tong Zhang 002 (CoRR, 2025)

Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure. - Rui Xie 006; Asad Ul Haq; Yunhua Fang; Linsen Ma; Sanchari Sen; Swagath Venkataramani; Liu Liu 017; Tong Zhang 002 (CoRR, 2025)

Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System. - Yunhua Fang; Rui Xie 006; Asad Ul Haq; Linsen Ma; Kaoutar El Maghraoui; Naigang Wang; Meng Wang; Liu Liu 017; Tong Zhang 002 (CoRR, 2025)