Analysis and Design of a Single-Stage Bridgeless Isolated AC-DC Resonant Converter for Programmable AC Power Source Applications. - Zhi Zhang 006; Junkai Wu; Liwei Meng; Zhaoyun Zhang; Xiao Tang 004; Bihua Hu; Wang Hu (IEEE Access, 2020)

An efficient pruning and fine-tuning method for deep spiking neural network. - Liwei Meng; Guanchao Qiao; Xiaoyang Zhang; Jian Bai; Yue Zuo; Pujun Zhou; Yang Liu 062; Shaogang Hu (Appl. Intell., 2023)

Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth. - Pujun Zhou; Yue Zuo; Guanchao Qiao; C. M. Zhang; Zhong Zhang 002; Liwei Meng; Qi Yu 002; Yang Liu 062; Shaogang Hu (IEEE Trans. Biomed. Circuits Syst., 2023)

Design of a Highly Flexible Hybrid Neural Network Inference Platform with 10 Million Neurons. - Yue Zuo; Ning Ning 002; K. Cao; R. Zhang; S. X. Wang; Liwei Meng; Guanchao Qiao; Y. Liu; Shaogang Hu (BioCAS, 2024)

A&B BNN: Add&Bit-Operation-Only Hardware-Friendly Binary Neural Network. - Ruichen Ma; Guanchao Qiao; Yian Liu 001; Liwei Meng; Ning Ning 002; Yang Liu 062; Shaogang Hu (CVPR, 2024)

A 0.96pJ/SOP, 30.23K-neuron/mm2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing. - Pujun Zhou; Qi Yu 002; M. Chen; Y. C. Wang; Liwei Meng; Yue Zuo; Ning Ning 002; Y. Liu; Shaogang Hu; Guanchao Qiao (ISCAS, 2024)

A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing. - Pujun Zhou; Qi Yu 002; M. Chen; Y. C. Wang; Liwei Meng; Yue Zuo; Ning Ning 002; Y. Liu; Shaogang Hu; Guanchao Qiao (CoRR, 2024)

YOLO-fall: a YOLO-based fall detection model with high precision, shrunk size, and low latency. - Xiaoyang Zhang; Jian Bai; Guanchao Qiao; Xiao Xiao; Liwei Meng; Shaogang Hu (Comput. J., 2025)

A Neuromorphic Transformer Architecture Enabling Hardware-Friendly Edge Computing. - Pujun Zhou; R. C. Ma; Y. C. Chen; Z. T. Liu; C. Y. Liu; Liwei Meng; Guanchao Qiao; Yang Liu 062; Qi Yu 002; Shaogang Hu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)