Logic BIST with Scan Chain Segmentation. - Liyang Lai; Janak H. Patel; Thomas Rinderknecht; Wu-Tung Cheng (ITC, 2004)

Logic BIST Using Constrained Scan Cells. - Liyang Lai; Thomas Rinderknecht; Wu-Tung Cheng; Janak H. Patel (VTS, 2004)

Hardware Ef.cient LBISTWith Complementary Weights. - Liyang Lai; Janak H. Patel; Thomas Rinderknecht; Wu-Tung Cheng (ICCD, 2005)

New Techniques for Logic Built -in Self -Test - Liyang Lai (2005)

Signature Based Diagnosis for Logic BIST. - Wu-Tung Cheng; Manish Sharma; Thomas Rinderknecht; Liyang Lai; Chris Hill (ITC, 2006)

Programmable Scan-Based Logic Built-In Self Test. - Liyang Lai; Wu-Tung Cheng; Thomas Rinderknecht (ATS, 2007)

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. - Jerzy Tyszer; Janusz Rajski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Mark Kassab; Wu-Tung Cheng; Manish Sharma; Liyang Lai (IEEE Des. Test Comput., 2007)

Detection and Diagnosis of Static Scan Cell Internal Defect. - Ruifeng Guo; Liyang Lai; Yu Huang 005; Wu-Tung Cheng (ITC, 2008)

STDF Memory Fail Datalog Standard. - Ajay Khoche; Jay Katz; Sauro Landini; Kochen Liao; Neetu Agrawal; Glenn Plowman; Songlin Zuo; Liyang Lai; John Rowe; Thomas Zanon (VTS, 2009)

Diagnosis and Layout Aware (DLA) Scan Chain Stitching. - Jing Ye 001; Yu Huang 005; Yu Hu 001; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li 001; Wei-pin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2015)

GPU-based Hybrid Parallel Logic Simulation for Scan Patterns. - Liyang Lai; Qiting Zhang; Kun-Han Hans Tsai; Wu-Tung Cheng (ITC-Asia, 2020)

GPGPU-Based ATPG System: Myth or Reality? - Liyang Lai; Kun-Han Tsai; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Scalable Parallel Static Learning. - Xiaoze Lin; Liyang Lai; Huawei Li 001 (ITC-Asia, 2021)

GPU-Based Concurrent Static Learning. - Huaxiao Liang; Xiaoze Lin; Liyang Lai; Naixing Wang; Yu Huang; Fei Yang; Yuxin Yang (ITC, 2023)

Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System. - Jingbo Hu; Guohao Dai; Liuzheng Wang; Liyang Lai; Yu Huang; Huazhong Yang; Yu Wang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Sideway Scan, Solving the Achilles' Heel of Scan-based Diagnosis. - Liyang Lai; Zefan Lin; Qitao Wang (ITC-Asia, 2024)

Parallel Static Learning Toward Heterogeneous Computing Architectures. - Xiaoze Lin; Liyang Lai; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core Systems. - Xiaoze Lin; Liyang Lai; Huawei Li; Biwei Xie; Xingquan Li (DATE, 2025)