CLUGGS and CLUCR-Two Matrix Solution Methods for General Circuit Simulation. - Bin Li; Liyi Xiao; Yizheng Ye; Guoyong Huang (Annual Simulation Symposium, 2001)

A mixed-signal simulator for VHDL-AMS. - Liyi Xiao; Bin Li; Yizheng Ye; Guoyong Huang; JinJun Guo; Peng Zhang (ASP-DAC, 2001)

A New Synchronization Algorithm for VHDL-AMS Simulation. - Liyi Xiao; Yizheng Ye; Bin Li (J. Comput. Sci. Technol., 2002)

A Test Architecture for System-on-a-Chip. - Yongsheng Wang; Liyi Xiao; Mingyan Yu; Jinxiang Wang 001; Yizheng Ye (Asian Test Symposium, 2003)

Electronic Shelf Label System based on public illuminating network. - Hong Hong; Yi Ren; Ricai Tian; Liyi Xiao (APCCAS, 2008)

A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata. - Bei Cao; Liyi Xiao; Yongsheng Wang (DELTA, 2008)

An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (DELTA, 2008)

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (ICECS, 2008)

Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (PRDC, 2008)

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (DAC, 2009)

Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory. - Ming Zhu; Liyi Xiao; Shuhao Li; Yanjing Zhang (DFT, 2010)

DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current. - Yu Sun; Liyi Xiao; Cong Shi (ISCAS, 2010)

New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory. - Ming Zhu; Liyi Xiao; Hong Wei Luo (VLSI-SoC, 2011)

Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping. - Bin Zhou; Liyi Xiao; Yizheng Ye; Xin-chun Wu (J. Electron. Test., 2011)

New Mix codes for multiple bit upsets mitigation in fault-secure memories. - Ming Zhu; Liyi Xiao; Li Li Song; Yan Jing Zhang; Hong Wei Luo (Microelectron. J., 2011)

Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost. - Bin Zhou; Liyi Xiao; Yizheng Ye; Xin-chun Wu; Bei Cao (J. Low Power Electron., 2012)

A Low Power Built-in Self-Test Scheme Based on Overlapping Bit Swapping Linear Feedback Shift Register. - Bin Zhou; Xin-chun Wu; Yu Sun; Tianqi Wang; Liyi Xiao (J. Low Power Electron., 2013)

Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs. - Jing Guo 004; Liyi Xiao; Zhigang Mao; Qiang Zhao (IEEE Micro, 2013)

CORDIC Based Fast Radix-2 DCT Algorithm. - Hai Huang; Liyi Xiao (IEEE Signal Process. Lett., 2013)

CORDIC-Based Unified Architectures for Computation of DCT/IDCT/DST/IDST. - Hai Huang; Liyi Xiao; Jiaming Liu (Circuits Syst. Signal Process., 2014)

CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation. - Hai Huang; Liyi Xiao (Microelectron. J., 2014)

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology. - Jing Guo 004; Liyi Xiao; Zhigang Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. - Jing Guo 004; Liyi Xiao; Zhigang Mao; Qiang Zhao (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Fault Secure Encoder and Decoder Designs for Matrix Codes. - Shanshan Liu 001; Liyi Xiao; Jing Guo 004; Zhigang Mao (CAD/Graphics, 2015)

Novel technique for P-hit single-event transient mitigation using enhance dummy transistor. - Tianqi Wang; Liyi Xiao; Mingxue Huo; Chunhua Qi; Shanshan Liu 001 (ISQED, 2015)

Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories. - Liyi Xiao; Jiaqiang Li; Jie Li 030; Jing Guo 004 (ISQED, 2015)

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology. - Chunhua Qi; Liyi Xiao; Jing Guo 004; Tianqi Wang (Microelectron. Reliab., 2015)

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology. - Jing Guo 004; Liyi Xiao; Tianqi Wang; Shanshan Liu 001; Xu Wang; Zhigang Mao (IEEE Trans. Reliab., 2015)

Extend orthogonal Latin square codes for 32-bit data protection in memory applications. - Shanshan Liu 001; Liyi Xiao; Zhigang Mao (Microelectron. Reliab., 2016)

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code. - Pedro Reviriego; Shanshan Liu 001; Liyi Xiao; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A method to estimate cross-section of circuits at RTL levels. - Liyi Xiao; Anlong Li; Xuebing Cao; Hongchen Li; Rongsheng Zhang; Jie Li 030; Tianqi Wang (ASICON, 2017)

Low-cost resilient radiation hardened flip-flop design. - Liyi Xiao; Chunhua Qi; Tianqi Wang; Hongchen Li; Jiaqiang Li (ASICON, 2017)

A fast and accurate fault injection platform for SRAM-based FPGAs. - Rongsheng Zhang; Liyi Xiao; Jie Li 030 (ASICON, 2017)

Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability. - Shanshan Liu 001; Liyi Xiao; Xuebing Cao; Zhigang Mao (ASP-DAC, 2017)

Low redundancy matrix-based codes for adjacent error correction with parity sharing. - Shanshan Liu 001; Liyi Xiao; Jie Li 030; Yihan Zhou; Zhigang Mao (ISQED, 2017)

A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications. - Chunhua Qi; Liyi Xiao; Mingxue Huo; Tianqi Wang; Rongsheng Zhang; Xuebing Cao (ISQED, 2017)

Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016). - Shanshan Liu 001; Pedro Reviriego; Alfonso Sánchez-Macián; Juan Antonio Maestro; Liyi Xiao (Microelectron. Reliab., 2017)

A method to recover critical bits under a double error in SEC-DED protected memories. - Shanshan Liu 001; Pedro Reviriego; Liyi Xiao; Juan Antonio Maestro (Microelectron. Reliab., 2017)

A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes. - Pedro Reviriego; Shanshan Liu 001; Alfonso Sánchez-Macián; Liyi Xiao; Juan Antonio Maestro (IEEE Trans. Reliab., 2017)

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology. - Jing Guo 004; Lei Zhu 004; Wenyi Liu; Hai Huang; Shanshan Liu 001; Tianqi Wang; Liyi Xiao; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Large Margin Structured Convolution Operator for Thermal Infrared Object Tracking. - Peng Gao 005; Yipeng Ma; Ke Song 002; Chao Li; Fei Wang 036; Liyi Xiao (ICPR, 2018)

Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm. - Xuebing Cao; Liyi Xiao; Linzhe Li; Jie Li 030; Jiaqiang Li; Jinxiang Wang 001 (IOLTS, 2018)

A Complementary Tracking Model with Multiple Features. - Peng Gao 005; Yipeng Ma; Ke Song 002; Chao Li; Fei Wang 036; Liyi Xiao (CoRR, 2018)

Adaptive Object Tracking with Complementary Models. - Peng Gao 005; Yipeng Ma; Chao Li; Ke Song 002; Yan Zhang 066; Fei Wang 036; Liyi Xiao (IEICE Trans. Inf. Syst., 2018)

High performance visual tracking with circular and structural operators. - Peng Gao 005; Yipeng Ma; Ke Song 002; Chao Li; Fei Wang 036; Liyi Xiao; Yan Zhang 066 (Knowl. Based Syst., 2018)

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes. - Shanshan Liu 001; Pedro Reviriego; Juan Antonio Maestro; Liyi Xiao (Microelectron. Reliab., 2018)

A fast fault injection platform of multiple SEUs for SRAM-based FPGAs. - Rongsheng Zhang; Liyi Xiao; Jie Li 030; Xuebing Cao; Chunhua Qi; Jiaqiang Li; Mingjiang Wang (Microelectron. Reliab., 2018)

Efficient Implementations of 4-Bit Burst Error Correction for Memories. - Jiaqiang Li; Liyi Xiao; Pedro Reviriego; Rongsheng Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications. - Jing Guo 004; Lei Zhu 004; Yu Sun; Huiliang Cao; Hai Huang; Tianqi Wang; Chunhua Qi; Rongsheng Zhang; Xuebing Cao; Liyi Xiao; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction. - Jiaqiang Li; Pedro Reviriego; Liyi Xiao; Costas Argyrides; Jie Li 030 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology. - Hongchen Li; Liyi Xiao; Jie Li 030; He Liu (ASICON, 2019)

Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit. - Linzhe Li; Liyi Xiao; Jie Li 030; He Liu; Zhigang Mao (ASICON, 2019)

A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network. - Jie Li 030; Liyi Xiao; Hongchen Li; Lulu Liao; Chenxu Wang (ASICON, 2019)

Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction. - Jiaqiang Li; Pedro Reviriego; Liyi Xiao; Alexander Klockmann (DFT, 2019)

Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells. - Shanshan Liu 001; Pedro Reviriego; Kazuteru Namba; Salvatore Pontarelli; Liyi Xiao; Fabrizio Lombardi (DFT, 2019)

Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs. - Xuebing Cao; Liyi Xiao; Linzhe Li; Jie Li 030; Tianqi Wang (ICICDT, 2019)

Learning Cascaded Siamese Networks for High Performance Visual Tracking. - Peng Gao 005; Yipeng Ma; Ruyue Yuan; Liyi Xiao; Fei Wang 036 (ICIP, 2019)

Efficient Concurrent Error Detection for SEC-DAEC Encoders. - Jiaqiang Li; Pedro Reviriego; Costas Argyrides; Liyi Xiao (IOLTS, 2019)

Single-event upset prediction in static random access memory cell account for parameter variations. - Mingxue Huo; Guoliang Ma; Bin Zhou; Liyi Xiao; Chunhua Qi; Yanqing Zhang 012; Jianning Ma; Yinghun Piao; Tianqi Wang (Sci. China Inf. Sci., 2019)

Siamese Attentional Keypoint Network for High Performance Visual Tracking. - Peng Gao 005; Yipeng Ma; Ruyue Yuan; Liyi Xiao; Fei Wang 036 (CoRR, 2019)

Learning Reinforced Attentional Representation for End-to-End Visual Tracking. - Peng Gao 005; Qiquan Zhang; Liyi Xiao; Yan Zhang 066; Fei Wang 036 (CoRR, 2019)

Low Delay 3-Bit Burst Error Correction Codes. - Jiaqiang Li; Pedro Reviriego; Liyi Xiao (J. Electron. Test., 2019)

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs). - Xuebing Cao; Liyi Xiao; Jie Li 030; Rongsheng Zhang; Shanshan Liu 001; Jinxiang Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes. - Pedro Reviriego; Shanshan Liu 001; Alfonso Sánchez-Macián; Liyi Xiao; Juan Antonio Maestro (DCIS, 2020)

Scheme for periodical concurrent fault detection in parallel CRC circuits. - Jie Li 030; Shanshan Liu 001; Pedro Reviriego; Liyi Xiao; Fabrizio Lombardi (IET Comput. Digit. Tech., 2020)

Learning reinforced attentional representation for end-to-end visual tracking. - Peng Gao 005; Qiquan Zhang; Fei Wang 036; Liyi Xiao; Hamido Fujita; Yan Zhang 066 (Inf. Sci., 2020)

Siamese attentional keypoint network for high performance visual tracking. - Peng Gao 005; Ruyue Yuan; Fei Wang 036; Liyi Xiao; Hamido Fujita; Yan Zhang 066 (Knowl. Based Syst., 2020)

An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA. - Rongsheng Zhang; Liyi Xiao; Jie Li 030; Xuebing Cao; Linzhe Li (IEEE Trans. Reliab., 2020)

Design of a high-performance 12T SRAM cell for single event upset tolerance. - Chunhua Qi; Yanqing Zhang 012; Guoliang Ma; Chaoming Liu; Tianqi Wang; Liyi Xiao; Mingxue Huo; Guofu Zhai (Sci. China Inf. Sci., 2021)

Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH). - Jie Li 030; Pedro Reviriego; Shanshan Liu 001; Liyi Xiao; Fabrizio Lombardi (Integr., 2021)

Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets. - Hongchen Li; Liyi Xiao; Chunhua Qi; Jie Li 030 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes. - Jiaqiang Li; Pedro Reviriego; Liyi Xiao; Haotian Wu (IEEE Trans. Emerg. Top. Comput., 2021)

A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors. - Jie Li 030; Liyi Xiao; Linzhe Li; Hongchen Li; He Liu; Chenxu Wang (IEEE Access, 2022)

Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits. - Linzhe Li; Liyi Xiao; He Liu; Zhigang Mao (IEEE Access, 2022)

A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs. - Jie Li 030; Liyi Xiao; Linzhe Li; Hongchen Li; He Liu; Chenxu Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Compact RF Energy Harvesting Wireless Sensor Node with an Energy Intensity Adaptive Management Algorithm. - Xiaoqiang Liu; Mingxue Li; Xinkai Chen; Yiheng Zhao; Liyi Xiao; Yufeng Zhang (Sensors, 2023)

SigDLA: A Deep Learning Accelerator Extension for Signal Processing. - Fangfa Fu; Wenyu Zhang; Zesong Jiang; Zhiyu Zhu; Guoyu Li; Bing Yang; Cheng Liu 008; Liyi Xiao; Jinxiang Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

SET-detection low complexity burst error correction codes for SRAM protection. - He Liu; Jiaqiang Li; Liyi Xiao; Tianqi Wang; Jie Li 030 (Integr., 2024)

Error Correction Codes for Double Burst Errors Correction in Memories. - He Liu; Liyi Xiao; Tianqi Wang; Jiaqiang Li; Jie Li 030 (IEEE Access, 2025)