Practical Challenges in Logic BIST Implementation. - Shianling Wu; Hiroshi Furukawa; Boryau Sheu; Laung-Terng Wang; Hao-Jan Chao; Lizhen Yu; Xiaoqing Wen; Michio Murakami (ATS, 2008)

Logic BIST Architecture for System-Level Test and Diagnosis. - Jun Qian; Xingang Wang; Qinfu Yang; Fei Zhuang; Junbo Jia; Xiangfeng Li; Yuan Zuo; Jayanth Mekkoth; Jinsong Liu; Hao-Jan Chao; Shianling Wu; Huafeng Yang; et al. (Asian Test Symposium, 2009)

A Measurement Device for the Dynamic Unbalance of Crankshaft. - Xiaoli Ye; Lizhen Yu; Zhiqin Shen (PACCS, 2009)

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Lizhen Yu; Hiroshi Furukawa; Xiaoqing Wen; Wen-Ben Jone; Nur A. Touba; FeiFei Zhao; Jinsong Liu; Hao-Jan Chao; Fangfang Li; Zhigang Jiang (DFT, 2010)

Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. - Lizhen Yu; Jeffrey Hung; Boryau Sheu; Bill Huynh; Loc Nguyen; Shianling Wu; Laung-Terng Wang; Xiaoqing Wen (DFT, 2010)

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Zhigang Jiang; Lang Tan; Yu Zhang; Yu Hu 001; Wen-Ben Jone; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Lizhen Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Physical-design-friendly hierarchical logic built-in self-test - A case study. - Kelvin Nelson; Jaga Shanmugavadivelu; Jayanth Mekkoth; Venkat Ghanta; Jun Wu; Fei Zhuang; Hao-Jan Chao; Shianling Wu; Jie Rao; Lizhen Yu; Laung-Terng Wang (ISQED, 2012)