RSIM: A circuit simulation program for VLSI interconnect networks. - Lloyd W. Massengill; Neal Bengtson (Simul., 1989)

Weight decay and resolution effects in feedforward artificial neural networks. - David Bryan Mundie; Lloyd W. Massengill (IEEE Trans. Neural Networks, 1991)

A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation. - Lloyd W. Massengill (IEEE J. Solid State Circuits, 1991)

An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control. - Lloyd W. Massengill; David Bryan Mundie (IEEE Trans. Neural Networks, 1992)

Design Technique for Mitigation of Soft Errors in Differential Switched-Capacitor Circuits. - Patrick R. Fleming; Brian D. Olson; W. Timothy Holman; Bharat L. Bhuva; Lloyd W. Massengill (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

The sensitivity of radiation-induced leakage to STI topology and sidewall doping. - Nadia Rezzak; Michael L. Alles; Ronald D. Schrimpf; Sarah Kalemeris; Lloyd W. Massengill; John Sochacki; Hugh J. Barnaby (Microelectron. Reliab., 2011)

Multi-cell soft errors at the 16-nm FinFET technology node. - N. Tam; Bharat L. Bhuva; Lloyd W. Massengill; Dennis R. Ball; Michael W. McCurdy; Michael L. Alles; Indranil Chatterjee (IRPS, 2015)

Impact of supply voltage and particle LET on the soft error rate of logic circuits. - Hui Jiang; H. Zhang; R. C. Harrington; J. A. Maharrey; J. S. Kauppila; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)

Designing soft-error-aware circuits with power and speed optimization. - H. Jiang; H. Zhang; Balaji Narasimham; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)

Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. - H. Zhang; H. Jiang; M. R. Eaker; Kurt J. Lezon; Balaji Narasimham; Nihaar N. Mahatme; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)

Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies. - Jingchen Cao; Lyuan Xu; Bharat L. Bhuva; Shi-Jie Wen; Richard Wong; Balaji Narasimham; Lloyd W. Massengill (IRPS, 2019)

Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology. - Lyuan Xu; Jingchen Cao; Bharat L. Bhuva; Indranil Chatterjee; Shi-Jie Wen; Richard Wong; Lloyd W. Massengill (IRPS, 2019)

Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology. - Jingchen Cao; Lyuan Xu; Shi-Jie Wen; Rita Fung; Balaji Narasimham; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2020)

Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node. - Yoni Xiong; Alexandra Feeley; Lloyd W. Massengill; Bharat L. Bhuva; Shi-Jie Wen; Rita Fung (IRPS, 2021)