Automatic pattern generation for the electrical characterization of digital modules. - Lluís Ribas; Jordi Riera; J. M. Pérez; Joaquín Saiz; Jordi Carrabina; Lluís Terés (Microprocess. Microprogramming, 1993)

A 60 ns 500×12 0.35µm CMOS low-power scanning read-out IC for cryogenic infra-red sensors. - Francisco Serra-Graells; Bertrand Misischi; Eduardo Casanueva; César Méndez; Lluís Terés (ISCAS (2), 2005)

A read-out strategy and circuit design for high frequency MEMS resonators. - Arantxa Uranga; Núria Barniol; Humberto Campanella; Jaume Esteve; Lluís Terés; Zachary Davis (ISCAS (6), 2005)

A current copying structure for current-mode monotonic digital-to-analog converters. - José Luis Merino; Lluís Terés; Jordi Carrabina (ISCAS, 2006)

A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers. - Francisco Serra-Graells; Josep Maria Margarit; Lluís Terés (ISCAS, 2007)

Low-Power and Compact CMOS APS Circuits for Hybrid Cryogenic Infrared Fast Imaging. - Francisco Serra-Graells; Bertrand Misischi; Eduardo Casanueva; César Méndez; Lluís Terés (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A novel DPS integrator for fast CMOS imagers. - Josep Maria Margarit; Justo Sabadell; Lluís Terés; Francisco Serra-Graells (ISCAS, 2008)

A Sub-µW fully programmable CMOS DPS for uncooled infrared fast imaging. - Josep Maria Margarit; Lluís Terés; Francisco Serra-Graells (ISCAS, 2008)

xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. - Jaume Joven; Oriol Font-Bach; David Castells-Rufas; Ricardo Martínez; Lluís Terés; Jordi Carrabina (PDP, 2008)

A Sub-muhboxW Fully Tunable CMOS DPS for Uncooled Infrared Fast Imaging. - Josep Maria Margarit; Lluís Terés; Francisco Serra-Graells (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Inkjet printed antennas for NFC systems. - Jordi Mujal; Eloi Ramon; Elkin Díaz; Jordi Carrabina; Álvaro Calleja; Ricardo Martínez; Lluís Terés (ICECS, 2010)

A self-biased PLL-tuned AER pixel for high-speed infrared imagers. - Josep Maria Margarit; Michele Dei; Lluís Terés; Francisco Serra-Graells (ISCAS, 2011)

A 70-mu m Pitch 8-mu W Self-Biased Charge-Integration Active Pixel for Digital Mammography. - Roger Figueras; Justo Sabadell; Lluís Terés; Francisco Serra-Graells (IEEE Trans. Biomed. Circuits Syst., 2011)

Teaching mixed-mode full-custom VLSI design with gaf, SpiceOpus and Glade. - Stepan Sutula; Francesc Vila; Jofre Pallares; Keith Sabine; Lluís Terés; Francisco Serra-Graells (EWME, 2014)

A 10kfps 32×32 integrated test platform for electrical characterization of imagers. - Josep Maria Margarit; Lluís Terés; Enric Cabruja; Francisco Serra-Graells (ISCAS, 2014)

A 25-µW All-MOS Potentiostatic Delta-Sigma ADC for Smart Electrochemical Sensors. - Stepan Sutula; Jofre Pallares Cuxart; Javier Gonzalo-Ruiz; Francesc Xavier Munoz-Pascual; Lluís Terés; Francisco Serra-Graells (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Printed microelectronics: From technology to design, rebuilding the path. - Eloi Ramon; Jordi Carrabina; Lluís Terés (EUROCON, 2015)

Class-AB single-stage OpAmp for low-power switched-capacitor circuits. - Stepan Sutula; Michele Dei; Lluís Terés; Francisco Serra-Graells (ISCAS, 2015)

A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR Applications. - Josep Maria Margarit; German Vergara; Victor Villamayor; Raul Gutierrez-Alvarez; Carlos Fernández-Montojo; Lluís Terés; Francisco Serra-Graells (IEEE J. Solid State Circuits, 2015)

A calibration-free 96.6-dB-SNDR non-bootstrapped 1.8-V 7.9-mW delta-sigma modulator with class-AB single-stage switched VMAs. - Stepan Sutula; Michele Dei; Lluís Terés; Francisco Serra-Graells (ISCAS, 2016)

Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits. - Stepan Sutula; Michele Dei; Lluís Terés; Francisco Serra-Graells (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers. - Michele Dei; Roger Figueras; Josep Maria Margarit; Lluís Terés; Francisco Serra-Graells (ISCAS, 2017)

A 10-bit linearity current-controlled ring oscillator with rolling regulation for smart sensing. - Michele Dei; Jordi Sacristán; Eloi Marigó; Mohanraj Soundara; Lluís Terés; Francisco Serra-Graells (ISCAS, 2017)

An academic EDA suite for the full-custom design of mixed-mode integrated circuits. - Jofre Pallares; Keith Sabine; Lluís Terés; Francisco Serra-Graells (ISCAS, 2017)

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation. - Michele Dei; Stepan Sutula; Jose Cisneros; Ernesto Pun; Richard Jan Engel Jansen; Lluís Terés; Francisco Serra-Graells (Sensors, 2017)

Inkjet-Configurable Gate Arrays (IGA). - Jordi Carrabina; Mohammad Mashayekhi; Jofre Pallares Cuxart; Lluís Terés (IEEE Trans. Emerg. Top. Comput., 2017)

A Compact Switched-Capacitor Multi-Bit Quantizer for Low-Power High-Resolution Delta-Sigma ADCs. - Jose Cisneros-Fernández; Francisco Serra-Graells; Lluís Terés; Michele Dei (ISCAS, 2018)

A 128× 128-pix 4-kfps 14-bit Digital-Pixel PbSe-CMOS Uncooled MWIR Imager. - Roger Figueras; Josep Maria Margarit; German Vergara; Victor Villamayor; Raúl Gutiérrez-Álvarez; Carlos Fernández-Montojo; Lluís Terés; Francisco Serra-Graells (ISCAS, 2018)

A 6.5-μW 70-dB 0.18-μm CMOS Potentiostatic Delta-Sigma for Electrochemical Sensors. - Joan Aymerich; Michele Dei; Lluís Terés; Francisco Serra-Graells (PRIME, 2018)

A 72-µW 90-dB Wide-Range Potentiostatic CMOS ΔΣ Modulator with Flicker Noise Cancellation for Smart Electrochemical Sensors. - Joan Aymerich; Michele Dei; Lluís Terés; Francisco Serra-Graells (ISCAS, 2019)

Switch-Less Frequency-Domain Multiplexing of GFET Sensors and Low-Power CMOS Frontend for 1024-Channel μECoG. - Jose Cisneros-Fernández; Michele Dei; Lluís Terés; Francisco Serra-Graells (ISCAS, 2019)

An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs. - Alejandro Suanes; Michele Dei; Lluís Terés; Francisco Serra-Graells (DCIS, 2020)

A 1024-Channel GFET 10-bit 5-kHz 36-μW Read-Out Integrated Circuit for Brain JLECoG. - Jose Cisneros-Fernández; Anton Guimerà-Brunet; Ramon Garcia-Cortadella; Nathan Schäfer; Jose A. Garrido; Lluís Terés; Francisco Serra-Graells (ICECS, 2020)

A 15-μW 105-dB 1.8-Vpp Potentiostatic Delta-Sigma Modulator for Wearable Electrochemical Transducers in 65-nm CMOS Technology. - Joan Aymerich; Augusto Márquez; Xavier Muñoz-Berbel; Francisco Javier del Campo; Gonzalo Guirado; Lluís Terés; Francisco Serra-Graells; Michele Dei (IEEE Access, 2020)

A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation. - Alejandro Suanes; Lluís Terés; Michele Dei; Francisco Serra-Graells (ISCAS, 2021)

A 1024-Channel 10-Bit 36-$ mu$W/ch CMOS ROIC for Multiplexed GFET-Only Sensor Arrays in Brain Mapping. - Jose Cisneros-Fernández; Ramon Garcia-Cortadella; Xavi Illa; Javier Martínez-Aguilar; Jens Paetzold; Rainer Mohrlok; Marius Kurnoth; Christoph Jeschke; Lluís Terés; Jose A. Garrido; Anton Guimerà-Brunet; Francisco Serra-Graells (IEEE Trans. Biomed. Circuits Syst., 2021)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

Processor Optimization of an Energy-Efficient NDIR CO2 Wireless Sensor Node. - Ricardo Núñez-Prieto; David Castells-Rufas; Narcís Avellana; Ricardo Martínez; Lluís Terés (DCIS, 2022)

A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs. - Alejandro Suanes; Michele Dei; Lluís Terés; Francisco Serra-Graells (Integr., 2022)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)

A Low-Power Neuromorphic CMOS Delta-Sigma Modulator Featuring Tunable Background Attenuation and Potentiostatic Asynchronous Readout for Smart Amperometric Electrochemical Sensors. - Javier Cuenca-Michans; Joan Aymerich; Lluís Terés; Cecilia Jiménez-Jorquera; Francisco Serra-Graells; Josep Maria Margarit-Taulé (ISCAS, 2023)