An Algorithm for Component Selection in Performance Optimized Scheduling. - Loganath Ramachandran; Daniel Gajski (ICCAD, 1991)

Semantics and synthesis of signals in behavioral VHDL. - Loganath Ramachandran; Frank Vahid; Sanjiv Narayan; Daniel D. Gajski (EURO-DAC, 1992)

High-Level Transformations for Minimizing Syntactic Variances. - Viraphol Chaiyakul; Daniel Gajski; Loganath Ramachandran (DAC, 1993)

Architectural tradeoffs in synthesis of pipelined controls. - Loganath Ramachandran; Daniel D. Gajski (EURO-DAC, 1993)

Synthesis of functions and procedures in behavioral VHDL. - Loganath Ramachandran; Sanjiv Narayan; Frank Vahid; Daniel D. Gajski (EURO-DAC, 1993)

An Algorithm for Array Variable Clustering. - Loganath Ramachandran; Daniel Gajski; Viraphol Chaiyakul (EDAC-ETC-EUROASIC, 1994)

100-hour design cycle: a test case. - Loganath Ramachandran; Daniel D. Gajski; Sanjiv Narayan; Frank Vahid; Peter Fung (EURO-DAC, 1994)

Introduction to High-Level Synthesis. - Daniel D. Gajski; Loganath Ramachandran (IEEE Des. Test Comput., 1994)

System design methodologies: aiming at the 100 h design cycle. - Daniel D. Gajski; Sanjiv Narayan; Loganath Ramachandran; Frank Vahid; Peter Fung (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Specification and Design of Multi-Million Gate SOCs. - Ramesh Chandra; Preeti Ranjan Panda; Jörg Henkel; Sri Parameswaran; Loganath Ramachandran (VLSI Design, 2003)