Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. - Loganathan Lingappan; Srivaths Ravi 001; Niraj K. Jha (ICCD, 2003)

Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. - Loganathan Lingappan; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha; Srimat T. Chakradhar (VLSI Design, 2005)

Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. - Loganathan Lingappan; Niraj K. Jha (VTS, 2005)

Test generation for combinational quantum cellular automata (QCA) circuits. - Pallav Gupta; Niraj K. Jha; Loganathan Lingappan (DATE, 2006)

Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. - Loganathan Lingappan; Niraj K. Jha (VLSI Design, 2006)

Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. - Loganathan Lingappan; Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. - Loganathan Lingappan; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha; Srimat T. Chakradhar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. - Loganathan Lingappan; Vijay Gangaram; Niraj K. Jha (VLSI Design, 2007)

Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. - Loganathan Lingappan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Test Generation Framework for Quantum Cellular Automata Circuits. - Pallav Gupta; Niraj K. Jha; Loganathan Lingappan (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. - Loganathan Lingappan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. - Loganathan Lingappan; Vijay Gangaram; Niraj K. Jha; Sreejit Chakravarty (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs. - Saparya Krishnamoorthy; Michael S. Hsiao; Loganathan Lingappan (Asian Test Symposium, 2010)

An Efficient 2-Phase Strategy to Achieve High Branch Coverage. - Sarvesh Prabhu; Michael S. Hsiao; Saparya Krishnamoorthy; Loganathan Lingappan; Vijay Gangaram; Jim Grundy (Asian Test Symposium, 2011)

Strategies for scalable symbolic execution-driven test generation for programs. - Saparya Krishnamoorthy; Michael S. Hsiao; Loganathan Lingappan (Sci. China Inf. Sci., 2011)

A Novel SMT-Based Technique for LFSR Reseeding. - Sarvesh Prabhu; Michael S. Hsiao; Loganathan Lingappan; Vijay Gangaram (VLSI Design, 2012)

A SMT-based diagnostic test generation method for combinational circuits. - Sarvesh Prabhu; Michael S. Hsiao; Loganathan Lingappan; Vijay Gangaram (VTS, 2012)

Test generation for circuits with embedded memories using SMT. - Sarvesh Prabhu; Michael S. Hsiao; Loganathan Lingappan; Vijay Gangaram (ETS, 2013)

Information-theoretic and statistical methods of failure log selection for improved diagnosis. - Sarmad Tanwir; Sarvesh Prabhu; Michael S. Hsiao; Loganathan Lingappan (ITC, 2015)

Hardware-in-the-loop model-less diagnostic test generation. - Sarmad Tanwir; Michael S. Hsiao; Loganathan Lingappan (HLDVT, 2016)

A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults. - Sarmad Tanwir; Michael S. Hsiao; Loganathan Lingappan (ACM Great Lakes Symposium on VLSI, 2017)

An online framework for diagnosis of multiple defects in scan chains. - Sarmad Tanwir; Michael S. Hsiao; Loganathan Lingappan (ISQED, 2018)

Online Scan Diagnosis : A Novel Approach to Volume Diagnosis. - I-De Huang; Pallav Gupta; Loganathan Lingappan; Vijay Gangaram (ITC, 2018)

Improved Silent Data Error Detection Through Test Optimization Using Reinforcement Learning. - Manu Shamsa; John D. Martin; Mariano Phielipp; Thiago Macieira; Loganathan Lingappan; Brad Kelly; David Lerner; Michael Tucknott; Ethan Hansen (IRPS, 2025)