Speeding up test pattern generation from behavioral VHDL descriptions containing several processes. - Loïc Vandeventer; Jean François Santucci (EURO-DAC, 1994)

Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructs. - Loïc Vandeventer; Jean François Santucci (EURO-DAC, 1994)

Using Binary Decision Diagrams to Speed up the Test Pattern Generation of Behavioral Circuit Descriptions Written in Hardware Description Languages. - Loïc Vandeventer; Jean François Santucci (ISCAS, 1994)

Speeding up behavioral test pattern generation using an algorithmic improvement. - Loïc Vandeventer; Jean François Santucci; Norbert Giambiasi (VTS, 1994)