Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 1999)

A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Great Lakes Symposium on VLSI, 1999)

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Joan Figueras; Salvador Manich; João Paulo Teixeira 001; Marcelino B. Santos (ISCAS (1), 1999)

A Test Vector Inhibiting Technique for Low Energy BIST Design. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (VTS, 1999)

An adjacency-based test pattern generator for low power BIST design. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2000)

Low power BIST design by hypergraph partitioning: methodology and architectures. - Patrick Girard 001; Christian Landrault; Loïs Guiller; Serge Pravossoudovitch (ITC, 2000)

Low Power BIST by Filtering Non-Detecting Vectors. - Salvador Manich; A. Gabarró; M. Lopez; Joan Figueras; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; João Paulo Teixeira 001; Marcelino B. Santos (J. Electron. Test., 2000)

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2001)

A Gated Clock Scheme for Low Power Scan-Based BIST. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (IOLTW, 2001)

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Hans-Joachim Wunderlich (VTS, 2001)

Integrating DFT in the Physical Synthesis Flow. - Loïs Guiller; Frederic Neuveux; S. Duggirala; R. Chandramouli; Rohit Kapur (ITC, 2002)

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (ITC, 2003)

Design of Routing-Constrained Low Power Scan Chains. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DELTA, 2004)

Power-Driven Routing-Constrained Scan Chain Design. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 2004)

A Gated Clock Scheme for Low Power Testing of Logic Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2006)