A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS. - Loke Kun Tan; Henry Samueli (IEEE J. Solid State Circuits, 1995)

An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS. - Loke Kun Tan; Edward W. Roth; Gordon E. Yee; Henry Samueli (IEEE J. Solid State Circuits, 1995)

A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder. - Loke Kun Tan; Jeffrey S. Putnam; Fang Lu; Lionel J. D'Luna; Dean W. Mueller; Kenneth R. Kindsfater; Kelly B. Cameron; Robindra B. Joshi; Robert A. Hawley; Henry Samueli (IEEE J. Solid State Circuits, 1998)

A single-chip universal cable set-top box/modem transceiver. - Lionel J. D'Luna; Loke Tan; Dean W. Mueller; Joe L. Laskowski; Kelly B. Cameron; Jind-Yeh Lee; David Gee; Jason S. Monroe; Honman S. Law; Jason Chang; Myles H. Wakayama; Tom Kwan; et al. (IEEE J. Solid State Circuits, 1999)

Correction to "A 70-Mb/s Variable-Rate 1024-QAM Cable Receiver IC with Integrated 10-b ADC and FEC Decoder". - Loke Kun Tan; Jeffrey S. Putnam; Fang Lu; Lionel J. D'Luna; Dean W. Mueller; Kenneth R. Kindsfater; Kelly B. Cameron; Robindra B. Joshi; Robert A. Hawley; Henry Samueli (IEEE J. Solid State Circuits, 1999)

An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0. - Francesco Gatta; Ray Gomez; Young Shin; Takayuki Hayashi; Hanli Zou; James Y. C. Chang; Leonard Dauphinee; Jianhong Xiao; Dave S.-H. Chang; Tai-Hong Chih; Massimo Brandolini; Dongsoo Koh; et al. (ISSCC, 2009)

An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0. - Francesco Gatta; Ray Gomez; Young J. Shin; Takayuki Hayashi; Hanli Zou; James Y. C. Chang; Leonard Dauphinee; Jianhong Xiao; Dave S.-H. Chang; Tai-Hong Chih; Massimo Brandolini; Dongsoo Koh; et al. (IEEE J. Solid State Circuits, 2009)

A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization. - Jiangfeng Wu; Chun-Ying Chen; Tianwei Li; Wenbo Liu; Lin He 006; Shauhyuarn Sean Tsai; Binning Chen; Chun-Sheng Huang; Juo-Jung Hung; Wei-Ta Shih; Hing T. Hung; Steven Jaffe; et al. (CICC, 2012)

A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization. - Jiangfeng Wu; Chun-Ying Chen; Tianwei Li; Lin He 006; Wenbo Liu; Wei-Ta Shih; Shauhyuarn Sean Tsai; Binning Chen; Chun-Sheng Huang; Bryan Juo-Jung Hung; Hing T. Hung; Steven Jaffe; et al. (IEEE J. Solid State Circuits, 2013)

A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver. - Jiangfeng Wu; Giuseppe Cusmai; Acer Wei-Te Chou; Tao Wang 010; Bo Shen; Vijayaramalingam Periasamy; Ming-Hung Hsieh; Chun-Ying Chen; Lin He 006; Loke Tan; Aravind Padyana; Cheng-Hsun Yang; et al. (VLSIC, 2015)

A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver. - Jiangfeng Wu; Giuseppe Cusmai; Acer Wei-Te Chou; Tao Wang 010; Bo Shen; Vijayaramalingam Periasamy; Ming-Hung Hsieh; Chun-Ying Chen; Lin He 006; Loke Kun Tan; Aravind Padyana; Vincent Cheng-Hsun Yang; et al. (IEEE J. Solid State Circuits, 2016)