Background calibration techniques for multistage pipelined ADCs with dynamic element matching and pseudorandom noise. - Longcheng Que; Yiying Du; Jian Lv; Yadong Jiang (ASICON, 2013)

Design of a high voltage gate driver module. - Longcheng Que; Jian Lv; Simon S. Ang (ASICON, 2015)

A high PSRR bandgap voltage reference with piecewise compensation. - Longcheng Que; Daogang Min; Linhai Wei; Yun Zhou; Jian Lv (Microelectron. J., 2020)

Robust and Efficient Registration of Infrared and Visible Images for Vehicular Imaging Systems. - Kai Che; Jian Lv; Jiayuan Gong; Jia Wei; Yun Zhou; Longcheng Que (Remote. Sens., 2024)