SAT and LP Collaborative Bounded Timing Analysis of Scenario-Based Specifications. - Longlong Lu; Wenhua Yang 001; Minxue Pan; Tian Zhang 001 (Internetware, 2020)

Improving timing analysis effectiveness for scenario-based specifications by combining SAT and LP techniques. - Longlong Lu; Minxue Pan; Tian Zhang 001; Xuandong Li (Softw. Syst. Model., 2022)

Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection. - Longlong Lu; Minxue Pan; Yifei Lu; Xuandong Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)