Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS. - Th. Calin; Lorena Anghel; Michael Nicolaidis (VTS, 1999)

Cost Reduction and Evaluation of a Temporary Faults Detecting Technique. - Lorena Anghel; Michael Nicolaidis (DATE, 2000)

Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy. - Lorena Anghel; Dan Alexandrescu; Michael Nicolaidis (SBCCI, 2000)

Self-Checking Circuits versus Realistic Faults in Very Deep Submicron. - Lorena Anghel; Michael Nicolaidis; Issam Alzaher-Noufal (VTS, 2000)

Les limites technologiques du silicium et tolérance aux fautes. (Fault tolerance versus technological limitations of silicon). - Lorena Anghel (2001)

New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. - Dan Alexandrescu; Lorena Anghel; Michael Nicolaidis (DFT, 2002)

Preliminary Validation of an Approach Dealing with Processor Obsolescence. - Lorena Anghel; Raoul Velazco; S. Saleh; S. Deswaertes; A. El Moucary (DFT, 2003)

A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities. - Michael Nicolaidis; Nadir Achouri; Lorena Anghel (DFT, 2003)

Memory Built-In Self-Repair for Nanotechnologies. - Michael Nicolaidis; Nadir Achouri; Lorena Anghel (IOLTS, 2003)

A Methodology for Test Replacement Solutions of Obsolete Processors. - Raoul Velazco; Lorena Anghel; S. Saleh (IOLTS, 2003)

Coupling Different Methodologies to Validate Obsolete Microprocessors. - Lorena Anghel; Ernesto Sánchez 001; Matteo Sonza Reorda; Giovanni Squillero; Raoul Velazco (DFT, 2004)

Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie. - Lorena Anghel; Nadir Achouri; Michael Nicolaidis (PRDC, 2004)

A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies. - Michael Nicolaidis; Nadir Achouri; Lorena Anghel (VTS, 2004)

Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. - Dan Alexandrescu; Lorena Anghel; Michael Nicolaidis (J. Electron. Test., 2004)

Evaluation of SET and SEU Effects at Multiple Abstraction Levels. - Lorena Anghel; Régis Leveugle; Pierre Vanhauwaert (IOLTS, 2005)

Simulation and Mitigation of Single Event Effects. - Lorena Anghel; Michael Nicolaidis (IOLTS, 2005)

On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. - Cristiano Lazzari; Lorena Anghel; Ricardo A. L. Reis (IOLTS, 2005)

A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. - Cristiano Lazzari; Lorena Anghel; Ricardo Reis 001 (VLSI-SoC, 2005)

Memory Defect Tolerance Architectures for Nanotechnologies. - Michael Nicolaidis; Lorena Anghel; Nadir Achouri (J. Electron. Test., 2005)

From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately? - Lorena Anghel; Michael Nicolaidis; Nadine Buard (IOLTS, 2006)

Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells. - Guillaume Hubert; Antonin Bougerol; Florent Miller; Nadine Buard; Lorena Anghel; Thierry Carrière; Frederic Wrobel; Rémi Gaillard (IOLTS, 2006)

Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. - Cristiano Lazzari; Ricardo A. L. Reis; Lorena Anghel (IOLTS, 2006)

Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies. - Lorena Anghel; Cristiano Lazzari; Michael Nicolaidis (LATW, 2006)

Essential Fault-Tolerance Metrics for NoC Infrastructures. - Cristian Grecu; Lorena Anghel; Partha Pratim Pande; André Ivanov; Resve A. Saleh (IOLTS, 2007)

Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells. - Claudia Rusu; Antonin Bougerol; Lorena Anghel; Cécile Weulersse; Nadine Buard; S. Benhammadi; Nicolas Renaud; Guillaume Hubert; Frederic Wrobel; Thierry Carrière; Rémi Gaillard (IOLTS, 2007)

Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies. - Lorena Anghel; Michael Nicolaidis (IWANN, 2007)

Efficient timing closure with a transistor level design flow. - Cristiano Lazzari; Cristiano Santos; Adriel Ziesemer; Lorena Anghel; Ricardo Reis 001 (VLSI-SoC, 2007)

A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. - Cristiano Lazzari; Ricardo A. L. Reis; Lorena Anghel (J. Electron. Test., 2007)

CNTFET Modeling and Reconfigurable Logic-Circuit Design. - Ian O'Connor; Junchen Liu; Frédéric Gaffiot; Fabien Prégaldiny; Christophe Lallement; Cristell Maneux; Johnny Goguet; Sébastien Fregonese; Thomas Zimmer; Lorena Anghel; Trong-Trinh Dang; Régis Leveugle (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems. - Claudia Rusu; Cristian Grecu; Lorena Anghel (DELTA, 2008)

Digital Implementation of a BIST Method based on Binary Observations. - Christophe Le Blanc; Éric Colinet; Jérôme Juillard; Lorena Anghel (DSD, 2008)

Communication Aware Recovery Configurations for Networks-on-Chip. - Claudia Rusu; Cristian Grecu; Lorena Anghel (IOLTS, 2008)

Improving the scalability of checkpoint recovery for networks-on-chip. - Claudia Rusu; Cristian Grecu; Lorena Anghel (ISCAS, 2008)

HOT TOPIC - Concurrent SoC development and end-to-end planning. - Lorena Anghel (DATE, 2009)

An effective approach to detect logic soft errors in digital circuits based on GRAAL. - Hai Yu; Michael Nicolaidis; Lorena Anghel (ISQED, 2009)

Error resilience of intra-die and inter-die communication with 3D spidergon STNoC. - Vladimir Pasca; Lorena Anghel; Claudia Rusu; Riccardo Locatelli; Massimo Coppola (DATE, 2010)

Fault tolerant communication in 3D integrated systems. - Vladimir Pasca; Lorena Anghel; Mounir Benabdenbi (DSN Workshops, 2010)

Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. - Vladimir Pasca; Lorena Anghel; Claudia Rusu; Mounir Benabdenbi (ETS, 2010)

Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems. - Michael Nicolaidis; Vladimir Pasca; Lorena Anghel (IOLTS, 2010)

Configurable serial fault-tolerant link for communication in 3D integrated systems. - Vladimir Pasca; Lorena Anghel; Claudia Rusu; Mounir Benabdenbi (IOLTS, 2010)

RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip. - Claudia Rusu; Lorena Anghel; Dimiter Avresky (IOLTS, 2010)

Bottom-up digital system-level reliability modeling. - N. Ruiz Amador; Vincent Huard; E. Pion; Florian Cacho; Damien Croain; V. Robert; Sylvain Engels; Philippe Flatresse; Lorena Anghel (CICC, 2011)

I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems. - Michael Nicolaidis; Vladimir Pasca; Lorena Anghel (ETS, 2011)

Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. - Hai Yu; Michael Nicolaidis; Lorena Anghel; Nacer-Eddine Zergainoh (ETS, 2011)

Memory BIST with address programmability. - Aymen Fradi; Michael Nicolaidis; Lorena Anghel (IOLTS, 2011)

Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis. - Vladimir Pasca; Lorena Anghel; Mounir Benabdenbi (LATW, 2011)

Adaptive inter-layer message routing in 3D networks-on-chip. - Claudia Rusu; Lorena Anghel; Dimiter Avresky (Microprocess. Microsystems, 2011)

Design for test and reliability in ultimate CMOS. - Michael Nicolaidis; Lorena Anghel; Nacer-Eddine Zergainoh; Yervant Zorian; Tanay Karnik; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Carlos Tokunaga; Arijit Raychowdhury; Muhammad M. Khellah; Jaydeep Kulkarni; et al. (DATE, 2012)

Efficient link-level error resilience in 3D NoCs. - Vladimir Pasca; Saif-Ur Rehman; Lorena Anghel; Mounir Benabdenbi (DDECS, 2012)

Through-silicon-via built-in self-repair for aggressive 3D integration. - Michael Nicolaidis; Vladimir Pasca; Lorena Anghel (IOLTS, 2012)

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis. - Vladimir Pasca; Lorena Anghel; Mounir Benabdenbi (J. Electron. Test., 2012)

CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems. - Vladimir Pasca; Lorena Anghel; Michael Nicolaidis; Mounir Benabdenbi (J. Electron. Test., 2012)

BIST for logic and local interconnect resources in a novel mesh of cluster FPGA. - Saif-Ur Rehman; Mounir Benabdenbi; Lorena Anghel (DFTS, 2013)

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. - Michael G. Dimopoulos; Yi Gang; Mounir Benabdenbi; Lorena Anghel; Nacer-Eddine Zergainoh; Michael Nicolaidis (IOLTS, 2013)

Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric. - Thomas Frank; Stéphane Moreau; Cédrick Chappaz; Patrick Leduc; Lucile Arnaud; Aurélie Thuaire; Emmanuel Chery; F. Lorut; Lorena Anghel; Gilles Poupon (Microelectron. Reliab., 2013)

System on chip project: Integration of a Motion-JPEG video decoder. - Lorena Anghel; Mounir Benabdenbi; Frédéric Pétrot (EWME, 2014)

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. - Andreas Steininger; Varadan Savulimedu Veeravalli; Dan Alexandrescu; Enrico Costenaro; Lorena Anghel (ICCD, 2014)

Cost-efficient of a cluster in a mesh SRAM-based FPGA. - Saif-Ur Rehman; Mounir Benabdenbi; Lorena Anghel (IOLTS, 2014)

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. - Saif-Ur Rehman; Adrien Blanchardon; Arwa Ben Dhia; Mounir Benabdenbi; Roselyne Chotin-Avot; Lirida A. B. Naviner; Lorena Anghel; Habib Mehrez; Emna Amouri; Zied Marrakchi (ISVLSI, 2014)

Editorial. - Lorena Anghel; Cristiana Bolchini; Salvatore Pontarelli (Microprocess. Microsystems, 2014)

Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. - Michael G. Dimopoulos; Yi Gang; Lorena Anghel; Mounir Benabdenbi; Nacer-Eddine Zergainoh; Michael Nicolaidis (Microprocess. Microsystems, 2014)

Timing in-situ monitors: Implementation strategy and applications results. - Ahmed Benhassain; Florian Cacho; Vincent Huard; M. Saliva; Lorena Anghel; C. R. Parthasarathy; Abhishek Jain 003; Fabien Giner (CICC, 2015)

Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI. - M. Saliva; Florian Cacho; Vincent Huard; X. Federspiel; D. Angot; Ahmed Benhassain; Alain Bravaix; Lorena Anghel (DATE, 2015)

Application-independent testing of multilevel interconnect in mesh-based FPGAs. - Saif-Ur Rehman; Mounir Benabdenbi; Lorena Anghel (DTIS, 2015)

Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology. - M. Saliva; Florian Cacho; Cheikh Ndiaye; Vincent Huard; D. Angot; Alain Bravaix; Lorena Anghel (IRPS, 2015)

Dependable Multicore Architectures at Nanoscale: The View From Europe. - Marco Ottavi; Salvatore Pontarelli; Dimitris Gizopoulos; Cristiana Bolchini; Maria K. Michael; Lorena Anghel; Mehdi Baradaran Tahoori; Antonis M. Paschalis; Pedro Reviriego; Oliver Bringmann 001; Viacheslav Izosimov; Hans A. R. Manhaeve; et al. (IEEE Des. Test, 2015)

Early failure prediction by using in-situ monitors: Implementation and application results. - Ahmed Benhassain; Florian Cacho; Vincent Huard; Lorena Anghel (ERMAVSS@DATE, 2016)

Study of workload impact on BTI HCI induced aging of digital circuits. - Ajith Sivadasan; Florian Cacho; Sidi Ahmed Benhassain; Vincent Huard; Lorena Anghel (DATE, 2016)

Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis. - Ajith Sivadasan; Florian Cacho; Sidi Ahmed Benhassain; Vincent Huard; Lorena Anghel (ERMAVSS@DATE, 2016)

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer. - Dan Alexandrescu; Mustafa Altun; Lorena Anghel; Anna Bernasconi 001; Valentina Ciriani; Luca Frontini; Mehdi Baradaran Tahoori (DSD, 2016)

A hybrid algorithm to conservatively check the robustness of circuits. - Niels Thole; Lorena Anghel; Görschwin Fey (ETS, 2016)

Activity profiling: Review of different solutions to develop reliable and performant design. - Florian Cacho; Ahmed Benhassain; Souhir Mhira; Ajith Sivadasan; Vincent Huard; P. Cathelin; Vincent Knopik; Abhishek Jain 003; C. R. Parthasarathy; Lorena Anghel (IOLTS, 2016)

In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability. - Ahmed Benhassain; Souhir Mhira; Florian Cacho; Vincent Huard; Lorena Anghel (IVSW, 2016)

Multi-context non-volatile content addressable memory using magnetic tunnel junctions. - Erya Deng; Lorena Anghel; Guillaume Prenat; Weisheng Zhao (NANOARCH, 2016)

Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results. - Lorena Anghel; Ahmed Benhassain; Ajith Sivadasan; Florian Cacho; Vincent Huard (VTS, 2016)

Workload dependent reliability timing analysis flow. - Ajith Sivadasan; Armelle Notin; Vincent Huard; Etienne Maurin; Souhir Mhira; Florian Cacho; Lorena Anghel (DATE, 2017)

Investigation of critical path selection for in-situ monitors insertion. - Florian Cacho; Ahmed Benhassain; Riddhi Jitendrakumar Shah; Souhir Mhira; Vincent Huard; Lorena Anghel (IOLTS, 2017)

Reliability analysis of MTJ-based functional module for neuromorphic computing. - Elena-Ioana Vatajelu; Lorena Anghel (IOLTS, 2017)

Fully-connected single-layer STT-MTJ-based spiking neural network under process variability. - Elena-Ioana Vatajelu; Lorena Anghel (NANOARCH, 2017)

Logic synthesis and testing techniques for switching nano-crossbar arrays. - Dan Alexandrescu; Mustafa Altun; Lorena Anghel; Anna Bernasconi 001; Valentina Ciriani; Luca Frontini; Mehdi Baradaran Tahoori (Microprocess. Microsystems, 2017)

NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI. - Ajith Sivadasan; Riddhi Jitendrakumar Shah; Vincent Huard; Florian Cacho; Lorena Anghel (DATE, 2018)

Resistive and Spintronic RAMs: Device, Simulation, and Applications. - Elena-Ioana Vatajelu; Lorena Anghel; Jean-Michel Portal; Marc Bocquet; Guillaume Prenat (IOLTS, 2018)

Investigation of speed sensors accuracy for process and aging compensation. - Riddhi Jitendrakumar Shah; Florian Cacho; Vincent Huard; Souhir Mhira; D. Arora; Pankaj Agarwal; Shubham Kumar; S. Balaraman; Bijoy Kumar Singh; Lorena Anghel (IRPS, 2018)

Integrated Synthesis Methodology for Crossbar Arrays. - Muhammed Ceylan Morgül; Onur Tunali; Mustafa Altun; Luca Frontini; Valentina Ciriani; Elena-Ioana Vatajelu; Lorena Anghel; Csaba Andras Moritz; Mircea R. Stan; Dan Alexandrescu (NANOARCH, 2018)

Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies. - Lorena Anghel; Denys Ly; Giorgio Di Natale; Benoît Miramond; Elena-Ioana Vatajelu; Elisa Vianello (VLSI-SoC, 2018)

Test and Reliability in Approximate Computing. - Lorena Anghel; Mounir Benabdenbi; Alberto Bosio; Marcello Traiola; Elena-Ioana Vatajelu (J. Electron. Test., 2018)

Hidden-Delay-Fault Sensor for Test, Reliability and Security. - Giorgio Di Natale; Elena-Ioana Vatajelu; Kalpana Senthamarai Kannan; Lorena Anghel (DATE, 2019)

Rebooting Computing: The Challenges for Test and Reliability. - Alberto Bosio; Ian O'Connor; Gennaro Severino Rodrigues; Fernanda Lima Kastensmidt; Elena I. Vatajelu; Giorgio Di Natale; Lorena Anghel; Surya Nagarajan; Moritz Fieback; Said Hamdioui (DFT, 2019)

Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints. - Sergiu Mosanu; Xinfei Guo; Mohamed El-Hadedy 001; Lorena Anghel; Mircea Stan (FCCM, 2019)

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model. - Lorena Anghel; Anna Bernasconi 001; Valentina Ciriani; Luca Frontini; Gabriella Trucco; Elena I. Vatajelu (LATS, 2019)

Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN). - Elena-Ioana Vatajelu; Giorgio Di Natale; Lorena Anghel (VTS, 2019)

A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. - Michele Portolan; R. Silveira Feitoza; Ghislain Takam Tchendjou; Vincent Reynaud; Kalpana Senthamarai Kannan; Manuel J. Barragán; Emmanuel Simeu; Paolo Maistri; Lorena Anghel; Régis Leveugle; Salvador Mir (IOLTS, 2020)

New Perspectives on Core In-field Path Delay Test. - Riccardo Cantoro; Dario Foti; Sandro Sartoni; Matteo Sonza Reorda; Lorena Anghel; Michele Portolan (ITC, 2020)

Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices. - Lorena Anghel; Anna Bernasconi 001; Valentina Ciriani; Luca Frontini; Gabriella Trucco; Elena I. Vatajelu (J. Electron. Test., 2020)

Zero-Overhead Protection for CNN Weights. - Stéphane Burel; Adrian Evans; Lorena Anghel (DFT, 2021)

Fast Behavioral VerilogA Compact Model for Stochastic MTJ. - Etienne Becle; Philippe Talatchian; Guillaume Prenat; Lorena Anghel; Ioan Lucian Prejbeanu (ESSDERC, 2021)

MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators. - Stéphane Burel; Adrian Evans; Lorena Anghel (IOLTS, 2021)

Monitoring Setup and Hold Timing Limits. - Florian Cacho; Lorena Anghel; Xavier Federspiel (IRPS, 2021)

Improving DNN Fault Tolerance in Semantic Segmentation Applications. - Stéphane Burel; Adrian Evans; Lorena Anghel (DFT, 2022)

Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks. - Manon Dampfhoffer; Thomas Mesquida; Alexandre Valentian; Lorena Anghel (ICANN (3), 2022)

Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network. - Kamal Danouchi; Guillaume Prenat; Lorena Anghel (LATS, 2022)

Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices. - Soyed Tuhin Ahmed; Kamal Danouchi; Christopher Münch; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (NANOARCH, 2022)

Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing. - Nhat-Tan Phan; Lucile Soumah; Ahmed Sidi El Valli; Louis Hutin; Lorena Anghel; Ursula Ebels; Philippe Talatchian (NANOARCH, 2022)

A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing. - Etienne Becle; Guillaume Prenat; Philippe Talatchian; Lorena Anghel; Ioan Lucian Prejbeanu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Design-Time Exploration for Process, Environment and Aging Compensation Techniques for Low Power Reliable-Aware Design. - Lorena Anghel; Florian Cacho (IEEE Trans. Emerg. Top. Comput., 2022)

Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (DATE, 2023)

Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. - Riccardo Cantoro; Sandro Sartoni; Matteo Sonza Reorda; Lorena Anghel; Michele Portolan (DFT, 2023)

On Using Cell-Aware Methodology for SRAM Bit Cell Testing. - Xhesila Xhafa; Aymen Ladhar; Eric Faehn; Lorena Anghel; Gregory di Pendina; Patrick Girard 001; Arnaud Virazel (ETS, 2023)

Leveraging Sparsity with Spiking Recurrent Neural Networks for Energy-Efficient Keyword Spotting. - Manon Dampfhoffer; Thomas Mesquida; Emmanuel Hardy; Alexandre Valentian; Lorena Anghel (ICASSP, 2023)

Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses. - Manon Dampfhoffer; Joel Minguet Lopez; Thomas Mesquida; Alexandre Valentian; Lorena Anghel (IJCNN, 2023)

Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging. - Yunus Emre Aslan; Florian Cacho; T. Kumar; D. K. Janardan; A. Kumar; F. Giner; M. Faurichon; Lorena Anghel (IOLTS, 2023)

Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits. - Kamal Danouchi; Guillaume Prenat; Philippe Talatchian; Louis Hutin; Lorena Anghel (ISVLSI, 2023)

A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. - Joao Henrique Quintino Palhares; Yann Beilliard; Jury Sandrini; Franck Arnaud; Kevin Garello; Guillaume Prenat; Lorena Anghel; Fabien Alibart; Dominique Drouin; Philippe Galy (CoRR, 2023)

Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (CoRR, 2023)

Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (CoRR, 2023)

SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation. - Soyed Tuhin Ahmed; Kamal Danouchi; Christopher Münch; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures. - Ghislain Takam Tchendjou; Kamal Danouchi; Guillaume Prenat; Lorena Anghel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Are SNNs Really More Energy-Efficient Than ANNs? an In-Depth Hardware-Aware Study. - Manon Dampfhoffer; Thomas Mesquida; Alexandre Valentian; Lorena Anghel (IEEE Trans. Emerg. Top. Comput. Intell., 2023)

SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (ACM Trans. Embed. Comput. Syst., 2023)

Self-Test Library Generation for In-Field Test of Path Delay Faults. - Lorena Anghel; Riccardo Cantoro; Riccardo Masante; Michele Portolan; Sandro Sartoni; Matteo Sonza Reorda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. - Soyed Tuhin Ahmed; Kamal Danouchi; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (DATE, 2024)

NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. - Soyed Tuhin Ahmed; Kamal Danouchi; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (DATE, 2024)

Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (ETS, 2024)

Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. - Soyed Tuhin Ahmed; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (CoRR, 2024)

Backpropagation-Based Learning Techniques for Deep Spiking Neural Networks: A Survey. - Manon Dampfhoffer; Thomas Mesquida; Alexandre Valentian; Lorena Anghel (IEEE Trans. Neural Networks Learn. Syst., 2024)

Low-Power Feature Extraction for BCI Applications Using Approximate Continuous Wavelet Transform. - Joe Saad; Adrian Evans; Ivan Miro-Panades; Tetiana Aksenova; Lorena Anghel (BCI, 2025)

Enabling a Portable Brain Computer Interface for Rehabilitation of Spinal Cord Injuries. - Adrian Evans; Victor Roux-Sibillon; Joe Saad; Ivan Miro-Panades; Tetiana Aksenova; Lorena Anghel (DATE, 2025)

Temperature and Drift-Aware High-Level PCM-based Array Model for Reliable Hardware IMC Design. - V. Viollet; E. Esmanhotto; M. Allegra; Matteo Baldo; Guillaume Prenat; Lorena Anghel; X. Lecoq (IRPS, 2025)