Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell. - Anis Feki; Bruno Allard; David Turgis; Jean-Christophe Lafont; Lorenzo Ciampolini (ISOCC, 2012)

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Sylvain Clerc; Lorenzo Ciampolini; Philippe Roche (ESSCIRC, 2013)

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI. - Kaya Can Akyel; Lorenzo Ciampolini; Olivier Thomas; Bertrand Pelloux-Prayer; Shishir Kumar; Philippe Flatresse; Christophe Lecocq; Gérard Ghibaudo (ISCAS, 2013)

Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI. - Kaya Can Akyel; Lorenzo Ciampolini; Olivier Thomas; David Turgis; Gérard Ghibaudo (ESSDERC, 2014)

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Anis Feki; Sylvain Clerc; Lorenzo Ciampolini; Fabien Giner; Robin Wilson; Philippe Roche (IEEE J. Solid State Circuits, 2014)

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. - Sylvain Clerc; Fady Abouzeid; Darayus Adil Patel; Jean-Marc Daveau; Cyril Bottoni; Lorenzo Ciampolini; Fabien Giner; David Meyer; Robin Wilson; Philippe Roche; Sylvie Naudet; Arnaud Virazel; et al. (ISQED, 2015)

A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI. - Babak Mohammadi; Oskar Andersson; Joseph Nguyen; Lorenzo Ciampolini; Andreia Cathelin; Joachim Neves Rodrigues (ESSCIRC, 2016)

Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells. - Lorenzo Ciampolini; Jean-Christophe Lafont; Faress Tissafi Drissi; Jean-Paul Morin; David Turgis; Xavier Jonsson; Cyril Desclèves; Joseph Nguyen (ICCAD, 2016)

RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs. - Joseph Nguyen; David Turgis; David Bonciani; Brice Lhomme; Yann Carminati; Olivier Callen; Guillaume Guirleo; Lorenzo Ciampolini; Gérard Ghibaudo (NATW, 2016)

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. - Rossella Ranica; Nicolas Planes; Vincent Huard; Olivier Weber; Daniel Noblet; Damien Croain; Fabien Giner; Sylvie Naudet; P. Mergault; S. Ibars; A. Villaret; Maryline Parra; et al. (VLSI Circuits, 2016)

High-yield design of high-density SRAM for low-voltage and low-leakage operations. - Kedar Janardan Dhori; Hitesh Chawla; Ashish Kumar; Prashant Pandey; Promod Kumar; Lorenzo Ciampolini; Florian Cacho; Damien Croain (DFT, 2017)

A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI. - Babak Mohammadi; Oskar Andersson; Joseph Nguyen; Lorenzo Ciampolini; Andreia Cathelin; Joachim Neves Rodrigues (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Storage Class Memory with Computing Row Buffer: A Design Space Exploration. - Valentin Egloff; Jean-Philippe Noel; Maha Kooli; Bastien Giraud; Lorenzo Ciampolini; Roman Gauchi; César Fuguet Tortolero; Eric Guthmuller; Mathieu Moreau; Jean-Michel Portal (DATE, 2021)

A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs. - Jean-Philippe Noel; Manuel Pezzin; Jean-Frédéric Christmann; Lorenzo Ciampolini; M. Le Coadou; M. Diallo; Florent Lepin; B. Blampey; Simone Bacles-Min; R. Wacquez; Bastien Giraud (ESSCIRC, 2021)

An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper. - A. Philippe; Lorenzo Ciampolini; A. Philippe; M. Gerbaud; M. Ramirez-Corrales; Valentin Egloff; Bastien Giraud; Jean-Philippe Noël (SLIP, 2022)