Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs. - Luca Ricci; Lorenzo Scaletti; Gabriele Bè; Luca Bertulessi; Salvatore Levantino; Carlo Samori; Andrea Bonfanti (ISCAS, 2022)

A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. - Lorenzo Scaletti; Gabriele Bè; Angelo Parisi; Luca Bertulessi; Luca Ricci; Mario Mercandelli; Salvatore Levantino; Carlo Samori; Andrea Bonfanti (NEWCAS, 2022)

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. - Gabriele Bè; Angelo Parisi; Luca Bertulessi; Luca Ricci; Lorenzo Scaletti; Mario Mercandelli; Andrea L. Lacaita; Salvatore Levantino; Carlo Samori; Andrea Bonfanti (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity. - Lorenzo Scaletti; Luca Bertulessi; Andrea Cristofoli; Andrea Bonfanti (NEWCAS, 2023)

A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. - Luca Ricci; Lorenzo Scaletti; Gabriele Bè; Michele Rocco; Luca Bertulessi; Salvatore Levantino; Andrea L. Lacaita; Carlo Samori; Andrea Bonfanti (VLSI Technology and Circuits, 2023)

A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization. - Gabriele Zanoletti; Lorenzo Scaletti; Gabriele Bè; Luca Ricci; Michele Rocco; Luca Bertulessi; Carlo Samori; Andrea Bonfanti (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk. - Luca Ricci; Gabriele Bè; Michele Rocco; Lorenzo Scaletti; Gabriele Zanoletti; Luca Bertulessi; Andrea L. Lacaita; Salvatore Levantino; Carlo Samori; Andrea Bonfanti (IEEE J. Solid State Circuits, 2025)