Evaluation of edge detectors performances with a discrete expression of Canny's criteria. - Didier Demigny; F. G. Lorca; Lounis Kessal (ICIP, 1995)

Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. - F. G. Lorca; Lounis Kessal; Didier Demigny (ICIP (2), 1997)

How to Use High Speed Reconfigurable FPGA for Real Time Image Processing? - Didier Demigny; Lounis Kessal; R. Bourguiba; N. Boudouani (CAMP, 2000)

Reconfigurable Hardware for Real Time Image Processing. - Lounis Kessal; Didier Demigny; N. Boudouani; R. Bourguiba (ICIP, 2000)

Fast Recursive Implementation of the Gaussian Filter. - Didier Demigny; Lounis Kessal; J. Pons (VLSI-SOC, 2001)

Reconfigurable Architecture Using High Speed FPGA. - Lounis Kessal; R. Bourguiba; Didier Demigny; N. Boudouani; Si Mahmoud Karabernou (VLSI-SOC, 2001)

Two ASIC for Low and Middle Levels of Real Time Image Processing. - P. Lamaty; B. Mazar; Didier Demigny; Lounis Kessal; Si Mahmoud Karabernou (VLSI-SOC, 2001)

Real-time image processing with dynamically reconfigurable architecture. - Lounis Kessal; Nicolas Abel; Didier Demigny (Real Time Imaging, 2003)

Design flexibility using fpga dynamical reconfiguration. - Nicolas Abel; Lounis Kessal; Didier Demigny (ICIP, 2004)

Clear Stream towards Dynamically Reconfigurable Systems on Chip. - Nicolas Abel; Lounis Kessal; Sébastien Pillement; Didier Demigny (ReCoSoC, 2006)

Erratum to "Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm" [Image and Vision Computing 23 (2005) 1009-1017]. - Si Mahmoud Karabernou; Lounis Kessal; Fayçal Terranti (Image Vis. Comput., 2007)

Neural network hardware architecture for pattern recognition in the HESS2 project. - Narayanan Ramanan; Sonia Khatchadourian; Jean-Christophe Prévotet; Lounis Kessal (ESANN, 2008)

Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing. - Lounis Kessal; Nicolas Abel; Si Mahmoud Karabernou; Didier Demigny (J. Real Time Image Process., 2008)

Hardware Architecture for Pattern Recognition in Gamma-Ray Experiment. - Sonia Khatchadourian; Jean-Christophe Prévotet; Lounis Kessal (EURASIP J. Embed. Syst., 2009)

Dataflow programming model for reconfigurable computing. - Laurent Gantel; Amel Khiar; Benoît Miramond; Mohamed El Amine Benkhelifa; Fabrice Lemonnier; Lounis Kessal (ReCoSoC, 2011)

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications. - Laurent Gantel; Amel Khiar; Benoît Miramond; Mohamed El Amine Benkhelifa; Lounis Kessal; Fabrice Lemonnier; Jimmy Le Rhun (ACM Trans. Reconfigurable Technol. Syst., 2012)

FPGA-implementation of a bio-inspired medical hearing aid based DWT-OLA. - Lotfi Bendaouia; Hassen Salhi; Si Mahmoud Karabernou; Lounis Kessal; Fayçal Ykhlef (ICAILP, 2014)

Density evolution thresholds for noise-against-noise min-sum decoders. - Franklin Cochachin; David Declercq; Emmanuel Boutillon; Lounis Kessal (PIMRC, 2017)

Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. - Khoa Le; Fakhreddine Ghaffari; Lounis Kessal; David Declercq; Valentin Savin; Oana Boncalo (ISCAS, 2018)

Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. - Khoa Le; David Declercq; Fakhreddine Ghaffari; Lounis Kessal; Oana Boncalo; Valentin Savin (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Position Paper: Prototyping Autonomous Vehicles Applications with Heterogeneous Multi-FpgaSystems. - Tarek Elouaret; Stéphane Zuckerman; Lounis Kessal; Yoan Espada; Nicolas Cuperlier; Guillaume Bresson; Fethi Ben Ouezdou; Olivier Romain (UCET, 2019)

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes. - Khoa Le; Fakhreddine Ghaffari; Lounis Kessal; David Declercq; Emmanuel Boutillon; Chris Winstead; Bane Vasic (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Implementation of a bio-inspired neural architecture for autonomous vehicle on a reconfigurable platform. - Tarek Elouaret; Sylvain Colomer; Frédéric Demelo; Nicolas Cuperlier; Olivier Romain; Lounis Kessal; Stéphane Zuckerman (ISIE, 2022)

Implementation of a Bio-Inspired Neural Architecture for Autonomous Vehicles on a Multi-FPGA Platform. - Tarek Elouaret; Sylvain Colomer; Frédéric de Melo; Nicolas Cuperlier; Olivier Romain; Lounis Kessal; Stéphane Zuckerman (Sensors, 2023)