Fast timing closure by interconnect criticality driven delay relaxation. - Love Singhal; Elaheh Bozorgzadeh (ICCAD, 2005)

Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. - Love Singhal; Elaheh Bozorgzadeh (FPL, 2006)

Physically-aware exploitation of component reuse in a partially reconfigurable architecture. - Love Singhal; Elaheh Bozorgzadeh (IPDPS, 2006)

Heterogeneous Floorplanner for FPGA. - Love Singhal; Elaheh Bozorgzadeh (FCCM, 2007)

Novel Multi-Layer floorplanning for Heterogeneous FPGAs. - Love Singhal; Elaheh Bozorgzadeh (FPL, 2007)

Multi-layer floorplanning for reconfigurable designs. - Love Singhal; Elaheh Bozorgzadeh (IET Comput. Digit. Tech., 2007)

Interconnect Criticality-Driven Delay Relaxation. - Love Singhal; Elaheh Bozorgzadeh; David Eppstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Statistical power profile correlation for realistic thermal estimation. - Love Singhal; Sejong Oh; Eli Bozorgzadeh (ASP-DAC, 2008)

Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors. - Love Singhal; Sejong Oh; Eli Bozorgzadeh (CODES+ISSS, 2008)

Process variation aware system-level task allocation using stochastic ordering of delay distributions. - Love Singhal; Elaheh Bozorgzadeh (ICCAD, 2008)

Process variation aware system-level load assignment for total energy minimization using stochastic ordering. - Shahin Golshan; Love Singhal; Eli Bozorgzadeh (ISQED, 2011)

Detailed placement for modern FPGAs using 2D dynamic programming. - Shounak Dhar; Saurabh N. Adya; Love Singhal; Mahesh A. Iyer; David Z. Pan (ICCAD, 2016)

LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs. - Love Singhal; Mahesh A. Iyer; Saurabh N. Adya (DAC, 2017)

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. - Shounak Dhar; Mahesh A. Iyer; Saurabh N. Adya; Love Singhal; Nikolay Rubanov; David Z. Pan (ISPD, 2017)

A shape-driven spreading algorithm using linear programming for global placement. - Shounak Dhar; Love Singhal; Mahesh A. Iyer; David Z. Pan (ASP-DAC, 2019)

FPGA Accelerated FPGA Placement. - Shounak Dhar; Love Singhal; Mahesh A. Iyer; David Z. Pan (FPL, 2019)

FPGA-Accelerated Spreading for Global Placement. - Shounak Dhar; Love Singhal; Mahesh A. Iyer; David Z. Pan (HPEC, 2019)

High-Definition Routing Congestion Prediction for Large-Scale FPGAs. - Mohamed Baker Alawieh; Wuxi Li; Yibo Lin; Love Singhal; Mahesh A. Iyer; David Z. Pan (ASP-DAC, 2020)