A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process. - Qian Zhou; Yan Han; Shifeng Zhang; Xiaoxia Han; Lu Jie 001; Ray C. C. Cheung; Guangtao Feng (Sci. China Inf. Sci., 2017)

A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC. - Nicholas Collins; Andres Tamez; Lu Jie 001; Jorge Pernillo; Michael P. Flynn (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC. - Lu Jie 001; Boyi Zheng; Michael P. Flynn (ISSCC, 2019)

Design Considerations for Integrated Radar Chirp Synthesizers. - Daniel Weyer; Mehmet Batuhan Dayanik; Lu Jie 001; Ahmed Albalawi; Abdulhamed Alothaimen; Mohammed Aseeri; Michael P. Flynn (IEEE Access, 2019)

A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC. - Lu Jie 001; Boyi Zheng; Michael P. Flynn (IEEE J. Solid State Circuits, 2019)

9.4 A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth. - Lu Jie 001; Boyi Zheng; Hsiang-Wen Chen; Runyu Wang; Michael P. Flynn (ISSCC, 2020)

A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension. - Lu Jie 001; Boyi Zheng; Hsiang-Wen Chen; Michael P. Flynn (IEEE J. Solid State Circuits, 2020)

TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping. - Boyi Zheng; Lu Jie 001; Michael P. Flynn (ESSCIRC, 2021)

10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer. - Lu Jie 001; Hsiang-Wen Chen; Boyi Zheng; Michael P. Flynn (ISSCC, 2021)

A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM. - Lu Jie 001; Hsiang-Wen Chen; Boyi Zheng; Michael P. Flynn (IEEE J. Solid State Circuits, 2021)

A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. - Wei Shi 011; Xing Wang; Xiyuan Tang; Abhishek Mukherjee; Raviteja Theertham; Shanthi Pavan; Lu Jie 001; Nan Sun 001 (CICC, 2022)

A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs. - Yunsong Tao; Kareem Ragab; Jin Shao; Pengpeng Chen; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISCAS, 2022)

A Second-Order VCO-Based ΔΣ ADC with Fully Digital Feedback Summation. - Chaoyang Xing; Yi Zhong; Jin Shao; Pengpeng Chen; Lu Jie 001; Nan Sun 001 (ISCAS, 2022)

A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR. - Lu Jie 001; Mingtao Zhan; Xiyuan Tang; Nan Sun 001 (ISSCC, 2022)

A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp. - Mingtao Zhan; Lu Jie 001; Xiyuan Tang; Nan Sun 001 (ISSCC, 2022)

An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (VLSI Technology and Circuits, 2022)

A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking. - Zhishuai Zhang; Zijie Gao; Siyu Huang; Nan Sun 001; Lu Jie 001 (CICC, 2023)

An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. - Yi Zhong; Mingtao Zhan; Wei Wang; Xiyuan Tang; Lu Jie 001; Nan Sun 001 (CICC, 2023)

A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration. - Mingyang Gu; Yunsong Tao; Xiyu He; Yi Zhong; Lu Jie 001; Nan Sun 001 (ESSCIRC, 2023)

A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors. - Mingyang Gu; Yi Zhong; Lu Jie 001; Nan Sun 001 (ESSCIRC, 2023)

A 0.021mm2 92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2nd-order RT-DEM and Quiet Chopping. - Chaoyang Xing; Yi Zhong; Nan Sun 001; Lu Jie 001 (ESSCIRC, 2023)

A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. - Zongnan Wang; Lu Jie 001; Zichen Kong; Mingtao Zhan; Yi Zhong; Yuan Wang 001; Xiyuan Tang (ISSCC, 2023)

A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor. - Mingtao Zhan; Lu Jie 001; Nan Sun 001 (ISSCC, 2023)

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. - Jinshan Yue; Mingtao Zhan; Zi Wang; Yifan He 002; Yaolei Li; Songming Yu; Wenyu Sun; Lu Jie 001; Chunmeng Dou; Xueqing Li 002; Nan Sun 001; Huazhong Yang; et al. (VLSI Technology and Circuits, 2023)

A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor. - Mingtao Zhan; Lu Jie 001; Yi Zhong; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators. - Mingyang Gu; Yunsong Tao; Xiyu He; Yi Zhong; Lu Jie 001; Nan Sun 001 (A-SSCC, 2024)

A 92.9dB-SNDR 178.2dB-FoMs SAR ADC with kT/C noise cancellation and FIA. - Zijie Gao; Yi Zhong; Lu Jie 001; Nan Sun 001 (ICTA, 2024)

A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs. - Yunsong Tao; Yi Zhong; Jin Shao; Changyou Men; Lu Jie 001; Nan Sun 001 (ISCAS, 2024)

9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs. - Xiyu He; Mingyang Gu; Hanjun Jiang; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISSCC, 2024)

22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration. - Yunsong Tao; Mingyang Gu; Baoyong Chi; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISSCC, 2024)

A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp. - Mingtao Zhan; Lu Jie 001; Xiyuan Tang; Yi Zhong; Nan Sun 001 (IEEE J. Solid State Circuits, 2024)

A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback. - Yanquan Luo; Lu Jie 001; Nan Sun 001 (CICC, 2025)

A 0.16mm2450MHz-BW 72dB-SNDR Continuous-time Pipeline ADC with APF+HPF and APF+FIR Hybrid Delay Alignment Techniques. - Heyang Zhao; Yuxuan He; Yunsong Tao; Zhishuai Zhang; Yong Chen 005; Yi Zhong; Lu Jie 001; Nan Sun 001 (CICC, 2025)

A 75-MHz-BW 3rd-order Time-Interleaved Noise-Shaping SAR ADC with Shared EF-CIFF Loop Filter and Ring Buffer. - Xiyu He; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISCAS, 2025)

A Hierarchical Compilation Method for Programmable Analog-to-Digital Converter Arrays. - Zhishuai Zhang; Siyu Huang; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISCAS, 2025)

Live Demonstration: A Programmable A/D Converter Array with Interactive Compiler. - Zhishuai Zhang; Chitian Yuan; Jiantao Li; Kun Lin; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISCAS, 2025)

24.1 A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration. - Mingyang Gu; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISSCC, 2025)

A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier. - Siyu Huang; Zhishuai Zhang; Xiyu He; Mingyang Gu; Yunsong Tao; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISSCC, 2025)

An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating. - Yunsong Tao; Mingtao Zhan; Mingyang Gu; Xiyu He; Yuxuan He; Zhishuai Zhang; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISSCC, 2025)

3.4: A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an on-Chip Heater-Based Self-Trimming Technique. - Aodong Zhang; Mingtao Zhan; Mengying Chen; Yi Zhong; Lu Jie 001; Nan Sun 001; Qinwen Fan (ISSCC, 2025)

A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration. - Mingyang Gu; Yunsong Tao; Xiyu He; Yi Zhong; Lu Jie 001; Nan Sun 001 (IEEE J. Solid State Circuits, 2025)

First-In-Last-Out Data Weighted Averaging Technique for Multi-Bit ΔΣ ADCs. - Xing Wang; Chaoyang Xing; Yi Zhong; Lu Jie 001; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (IEEE J. Solid State Circuits, 2025)