An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write Assist. - Lu Lu 013; Taegeun Yoo; Van Loi Le; Tony Tae-Hyoung Kim (A-SSCC, 2018)

A Sequence-Dependent Configurable PUF Based on 6T SRAM for Enhanced Challenge Response Space. - Lu Lu 013; Tony Tae-Hyoung Kim (ISCAS, 2019)

Improving uniformity and reliability of SRAM PUFs utilizing device aging phenomenon for unique identifier generation. - Achiranshu Garg; Zhao Chuan Lee; Lu Lu 013; Tony Tae-Hyoung Kim (Microelectron. J., 2019)

ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology. - Lu Lu 013; Ju Eon Kim; Vishal Sharma 004; Tony Tae-Hyoung Kim (APCCAS, 2020)

Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (ISCAS, 2020)

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines. - Lu Lu 013; Taegeun Yoo; Van Loi Le; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Programmable 6T SRAM-Based PUF with Dynamic Stability Data Masking. - Lu Lu 013; Tony Tae-Hyoung Kim (A-SSCC, 2021)

A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory. - Yuzong Chen 001; Lu Lu 013; Yuncheng Lu; Tony Tae-Hyoung Kim (ISCAS, 2021)

A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme. - Lu Lu 013; Yuzong Chen 001; Tony Tae-Hyoung Kim (ISCAS, 2021)

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (IEEE Open J. Circuits Syst., 2021)

A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory. - Yuzong Chen 001; Junjie Mu; Hyunjoon Kim; Lu Lu 013; Tony Tae-Hyoung Kim (ISCAS, 2022)

Temperature Compensation on SRAM-Based Computation in Memory Array. - Qibang Zang; Wang Ling Goh; Fei Li 015; Lu Lu 013; Anh Tuan Do (ISOCC, 2022)

A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices. - Vishal Sharma 004; Ju Eon Kim; Hyunjoon Kim; Lu Lu 013; Tony Tae-Hyoung Kim (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices. - Lu Lu 013; Taegeun Yoo; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A High Reliable SRAM-Based PUF With Enhanced Challenge-Response Space. - Lu Lu 013; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips. - Lu Lu 013; Aarthy Mani; Anh Tuan Do (ISCAS, 2023)

282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. - Qibang Zang; Wang Ling Goh; Lu Lu 013; Chengshuo Yu; Junjie Mu; Tony Tae-Hyoung Kim; Bongjin Kim; Dongrui Li; Anh Tuan Do (ISCAS, 2023)

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory. - Yuzong Chen 001; Junjie Mu; Hyunjoon Kim; Lu Lu 013; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications. - Lu Lu 013; Anh-Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation. - Junjie Mu; Lu Lu 013; Ju Eon Kim; Byung-Kwon An; Vishal Sharma 004; Arya Jagath Lekshmi; Putu Andhita Dananjaya; Weng Hong Lai; Wen Siang Lew; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)