CAD Tools for the optimized design of custom VLSI wave digital filters. - Rajeev Jain; Gert Goossens; Luc J. M. Claesen; Joos Vandewalle; Hugo De Man; L. Gazsi; Alfred Fettweis (ICASSP, 1985)

An intelligent module generator environment. - Paul Six; Luc J. M. Claesen; Jan M. Rabaey; Hugo De Man (DAC, 1986)

Cathedral-II: A Silicon Compiler for Digital Signal Processing. - Hugo De Man; Jan M. Rabaey; Paul Six; Luc J. M. Claesen (IEEE Des. Test, 1986)

Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. - Ivo Bolsens; W. De Rammelaere; Luc J. M. Claesen; Hugo De Man (DAC, 1989)

Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. - Patrick Odent; Luc J. M. Claesen; Hugo De Man (DAC, 1989)

Static Timing Analysis of Dynamically Sensitizable Paths. - S. Perremans; Luc J. M. Claesen; Hugo De Man (DAC, 1989)

Correctness verification of VLSI modules supported by a very efficient Boolean prover. - P. Lammens; Luc J. M. Claesen; Hugo De Man (ICCD, 1989)

Efficient false path elimination algorithms for timing verification by event graph preprocessing. - Luc J. M. Claesen; J. P. Schupp; P. Das; P. Johannes; S. Perremans; Hugo De Man (Integr., 1989)

Application of system semantics to VLSI for the transformational design of a parameterized booth multiplier module - a case study. - Luc Claesen; R. T. Boute; J. De Man; W. Ploegaerts; M. Seutter; J. Vanslembrouck; Diederik Verkest (Microprocessing and Microprogramming, 1989)

Description and verification of more-dimensional regular and non-homogeneous structures using a functional hardware description language. - W. Ploegaerts; Diederik Verkest; Luc Claesen; Hugo De Man (Microprocessing and Microprogramming, 1989)

SLOCOP-II: a versatile timing verification system for MOSVLSI. - P. Johannes; P. Das; Luc J. M. Claesen; Hugo De Man (EURO-DAC, 1990)

A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation. - Patrick Odent; Luc J. M. Claesen; Hugo De Man (EURO-DAC, 1990)

SPI: an open interface integrating highly interactive electronic CAD tools. - J. P. Schupp; Johan Cockx; Luc J. M. Claesen; Hugo De Man (EURO-DAC, 1990)

Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment. - Diederik Verkest; Luc J. M. Claesen; Hugo De Man (EURO-DAC, 1990)

Derivation of signal flow direction in MOS VLSI: an alternative. - W. De Rammelaere; Ivo Bolsens; Luc J. M. Claesen; Hugo De Man (ICCD, 1990)

Timing verification using statically sensitizable paths. - Jacques Benkoski; E. Vanden Meersch; Luc J. M. Claesen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Acceleration of relaxation-based circuit simulation using a multiprocessor system. - Patrick Odent; Luc J. M. Claesen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II. - Mark Genoe; Luc J. M. Claesen; Eric Verlind; Frank Proesmans; Hugo De Man (ICCD, 1991)

Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis. - Catia M. Angelo; Diederik Verkest; Luc J. M. Claesen; Hugo De Man (TPHOLs, 1991)

Defining Recursive Functions in HOL. - W. Ploegaerts; Luc J. M. Claesen; Hugo De Man (TPHOLs, 1991)

ASICs for a High Performance IVIulti Processor Systemfor Photo-realistic Image Synthesis. - Peter De Vijt; Luc J. M. Claesen; Hugo De Man (Eurographics Workshop on Graphics Hardware, 1992)

On the use of hierarchy in timing verification with statically sensitizable paths. - P. Johannes; Luc J. M. Claesen; Hugo De Man (Great Lakes Symposium on VLSI, 1992)

Performance Through Hierarchy in Static Timing Verification. - P. Johannes; Luc J. M. Claesen; Hugo De Man (IFIP Congress (1), 1992)

A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU. - Diederik Verkest; Luc J. M. Claesen; Hugo De Man (Designing Correct Circuits, 1992)

A Description Methodology for Parameterized Modules in the Boyer-Moore Logic. - Diederik Verkest; J. Vandenbergh; Luc J. M. Claesen; Hugo De Man (TPCD, 1992)

The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL. - Catia M. Angelo; Luc J. M. Claesen; Hugo De Man (TPHOLs, 1992)

An Architecture for Ray - Bezier Patch Intersection. - Peter De Vijt; Luc J. M. Claesen; Hugo De Man (Workshop on Graphics Hardware, 1993)

Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip. - Luc J. M. Claesen; Joan Daemen; Mark Genoe; G. Peeters (ICCD, 1993)

Degrees of Formality in Shallow Embedding Hardware Description Languages in HOL. - Catia M. Angelo; Luc J. M. Claesen; Hugo De Man (HUG, 1993)

On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification. - Catia M. Angelo; Diederik Verkest; Luc J. M. Claesen; Hugo De Man (Formal Methods Syst. Des., 1993)

A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis. - Mark Genoe; Luc J. M. Claesen; Hugo De Man (ICCD, 1994)

Reasoning About a Class of Linear Systems of Equations in HOL. - Catia M. Angelo; Luc J. M. Claesen; Hugo De Man (TPHOLs, 1994)

Modeling Multi-rate DSP Specification Semantics for Formal Transformational Design in HOL. - Catia M. Angelo; Luc J. M. Claesen; Hugo De Man (Formal Methods Syst. Des., 1994)

A Proof of the Nonrestoring Division Algorithm and its Implementation on an ALU. - Diederik Verkest; Luc J. M. Claesen; Hugo De Man (Formal Methods Syst. Des., 1994)

ED&TC 1995: Simulation versus formal verification. - Luc J. M. Claesen (IEEE Des. Test Comput., 1995)

A formal verification technique for embedded software. - Olivier Thiry; Luc J. M. Claesen (ICCD, 1996)

On-line signature verification by dynamic time-warping. - Ronny Martens; Luc J. M. Claesen (ICPR, 1996)

An Evaluation of Different Handwriting Observation Techniques from a Signature Verification Point of View. - Ronny Martens; Luc J. M. Claesen (BSDIA, 1997)

A symbolic core approach to the formal verification of integrated mixed-mode applications. - Stefan Hendricx; Luc J. M. Claesen (ED&TC, 1997)

Dynamic Programming Optimisation for On-line Signature Verificatio. - Ronny Martens; Luc J. M. Claesen (ICDAR, 1997)

On-line Signature Verification: Discrimination Emphasised. - Ronny Martens; Luc J. M. Claesen (ICDAR, 1997)

Incorporating local consistency information into the online signature verification process. - Ronny Martens; Luc J. M. Claesen (Int. J. Document Anal. Recognit., 1998)

Verification of Finite-State-Machine Refinements Using a Symbolic Methodology. - Stefan Hendricx; Luc J. M. Claesen (CHARME, 1999)

Formally Verified Redundancy Removal. - Stefan Hendricx; Luc J. M. Claesen (DATE, 1999)

Symbolic Multi-Level Verification of Refinement. - Stefan Hendricx; Luc J. M. Claesen (Great Lakes Symposium on VLSI, 1999)

Dip - it: digital infrared painting on an interactive table. - Peter Vandoren; Tom Van Laerhoven; Luc Claesen; Johannes Taelman; Fabian Di Fiore; Frank Van Reeth; Eddy Flerackers (CHI Extended Abstracts, 2008)

IntuPaint: Bridging the gap between physical and digital painting. - Peter Vandoren; Tom Van Laerhoven; Luc Claesen; Johannes Taelman; Chris Raymaekers; Frank Van Reeth (Tabletop, 2008)

FluidPaint: an interactive digital painting system using real wet brushes. - Peter Vandoren; Luc Claesen; Tom Van Laerhoven; Johannes Taelman; Chris Raymaekers; Eddy Flerackers; Frank Van Reeth (ITS, 2009)

An on-chip parallel memory architecture for a stereo vision system. - Andy Motten; Luc Claesen (ICECS, 2010)

SoC architecture for real-time interactive painting based on lattice-Boltzmann. - Domien Nowicki; Luc Claesen (ICECS, 2010)

Smart Camera System-on-Chip Architecture for Real-Time Brush Based Interactive Painting Systems. - Luc Claesen; Peter Vandoren; Tom Van Laerhoven; Andy Motten; Fabian Di Fiore; Frank Van Reeth; Jing Liao 001; Jinhui Yu (VLSI-SoC (Selected Papers), 2010)

Smart camera SoC system for interactive real-time real-brush based digital painting systems. - Luc Claesen; Peter Vandoren; Tom Van Laerhoven; Andy Motten; Domien Nowicki; Tom De Weyer; Frank Van Reeth; Eddy Flerackers (VLSI-SoC, 2010)

A binary adaptable window SoC architecture for a stereo vision based depth field processor. - Andy Motten; Luc Claesen (VLSI-SoC, 2010)

Binary confidence evaluation for a stereo vision based depth field processor SoC. - Andy Motten; Luc Claesen; Yun Pan (ACPR, 2011)

Adaptive memory architecture for real-time image warping. - Andy Motten; Luc Claesen; Yun Pan (ICCD, 2012)

Trinocular disparity processor using a hierarchic classification structure. - Andy Motten; Luc Claesen; Yun Pan (VLSI-SoC, 2012)

Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure. - Andy Motten; Luc Claesen; Yun Pan (VLSI-SoC (Selected Papers), 2012)

A Fast Self-Organizing Map Algorithm for Handwritten Digit Recognition. - Yimu Wang; Alexander Peyls; Yun Pan; Luc Claesen; Xiaolang Yan (MUE, 2013)

A spatiotemporal dithering method to extend color depth in multi-display system. - Yimu Wang; Luc Claesen (ICSAI, 2014)

SoC processor for real-time object labeling in life camera streams with low line level latency. - Zhengqiang Yu; Luc Claesen; Yun Pan; Andy Motten; Yimu Wang; Xiaolang Yan (ISCAS, 2014)

Comparison of Predictive-Corrective Video Coding Filters for Real-Time FPGA-based Lossless Compression in Multi-Camera Systems. - Bart Stukken; Yimu Wang; Yu Bao; Caikou Chen; Luc Claesen (FPGAworld, 2015)

Quantitative comparison of lossless video compression for multi-camera stereo and view interpolation applications. - Yu Bao; Bart Stukken; Jef Stals; Caikou Chen; Luc Claesen (NEWCAS, 2015)

Cloud-based orthognathic surgical planning platform. - Wout Swinkels; Yi Sun; Bart Stukken; Constantinus Politis; Luc Claesen (NEWCAS, 2015)

SoC and FPGA oriented high-quality stereo vision system. - Yanzhe Li; Kai Huang 002; Luc Claesen (FPL, 2016)

Poster: A Software-Defined Multi-Camera Network. - Po-Yen Chen; Chien Chen; Parthiban Selvaraj; Luc Claesen (MobiSys (Companion Volume), 2016)

Line buffer reduction for LUT-based real-time image inverse warping. - Yufeng Lu; Xiaohua Luo; Yimu Wang; Luc Claesen (NEWCAS, 2016)

SoC oriented real-time high-quality stereo vision system. - Yanzhe Li; Kai Huang 002; Luc Claesen (VLSI-SoC, 2016)

A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA. - Yanzhe Li; Kai Huang 002; Luc Claesen (VLSI-SoC (Selected Papers), 2016)

CT-based automatic identification and localization of the right phrenic nerve. - Kobe Bamps; Celine Cuypers; Luc Claesen; Pieter Koopman (CISP-BMEI, 2017)

Automated winston-lutz test for efficient quality control in stereotactic radiosurgery. - Michiel Darcis; Gert Leurs; Kenny Geens; Alexandra Jankelevitch; Wout Swinkels; Luc Claesen (CISP-BMEI, 2017)

Haptic collision detection on highly complex medical data structures. - Niels Pirotte; Casper Vranken; Wout Swinkels; Luc Claesen; Yi Sun; Constantinus Politis (CISP-BMEI, 2017)

Real-time SVM-based emotion recognition algorithm. - Wout Swinkels; Luc Claesen; Feng Xiao; Haibin Shen (CISP-BMEI, 2017)

SVM point-based real-time emotion detection. - Wout Swinkels; Luc Claesen; Feng Xiao; Haibin Shen (DSC, 2017)

High-quality view interpolation based on depth maps and its hardware implementation. - Yanzhe Li; Kai Huang 002; Luc Claesen (FPL, 2017)

PoseLab: A Levenberg-Marquardt Based Prototyping Environment for Camera Pose Estimation. - Michiel Darcis; Wout Swinkels; Aydin Emre Guzel; Luc Claesen (CISP-BMEI, 2018)

Analysis of Collision Detection Using Implicit Sphere Tree in Saptic Interaction Environments for Maxillofacial Surgery Applications. - Laurens Le Jeune; Wout Swinkels; Yi Sun; Constantinus Politis; Luc Claesen (CISP-BMEI, 2018)

A Real-Time High-Quality Complete System for Depth Image-Based Rendering on FPGA. - Yanzhe Li; Luc Claesen; Kai Huang 002; Menglian Zhao (IEEE Trans. Circuits Syst. Video Technol., 2019)

DFQF: Data Free Quantization-aware Fine-tuning. - Bowen Li 017; Kai Huang 002; Siang Chen; Dongliang Xiong; Haitian Jiang; Luc Claesen (ACML, 2020)

Adaptive Hybrid Composition Based Super-Resolution Network via Fine-Grained Channel Pruning. - Siang Chen; Kai Huang 002; Bowen Li 017; Dongliang Xiong; Haitian Jiang; Luc Claesen (ECCV Workshops (3), 2020)

Fine-Grained Channel Pruning for Deep Residual Neural Networks. - Siang Chen; Kai Huang 002; Dongliang Xiong; Bowen Li 017; Luc Claesen (ICANN (2), 2020)

Fast Incremental Least Square Pose Estimation for Hardware Implementation with Rolling Shutter Camera. - Aydin Emre Güzel; Dilara Hisar; Luc Claesen; H. Fatih Ugurdag (SIU, 2020)

A novel feature representation: Aggregating convolution kernels for image retrieval. - Qi Wang 079; Jinxing Lai; Luc Claesen; Zhenguo Yang; Liang Lei; Wenyin Liu (Neural Networks, 2020)

DPOQ: Dynamic Precision Onion Quantization. - Bowen Li 017; Kai Huang 002; Siang Chen; Dongliang Xiong; Luc Claesen (ACML, 2021)

Sample-wise dynamic precision quantization for neural network acceleration. - Bowen Li 017; Dongliang Xiong; Kai Huang 002; Xiaowen Jiang 001; Hao Yao; Junjian Chen; Luc Claesen (IEICE Electron. Express, 2022)

Structured precision skipping: Accelerating convolutional neural networks with budget-aware dynamic precision selection. - Kai Huang 002; Siang Chen; Bowen Li 017; Luc Claesen; Hao Yao; Junjian Chen; Xiaowen Jiang 001; Zhili Liu; Dongliang Xiong (J. Syst. Archit., 2022)

Acceleration-Aware Fine-Grained Channel Pruning for Deep Neural Networks via Residual Gating. - Kai Huang 002; Siang Chen; Bowen Li 017; Luc Claesen; Hao Yao; Junjian Chen; Xiaowen Jiang 001; Zhili Liu; Dongliang Xiong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

ClueDepth Grasp: Leveraging positional clues of depth for completing depth of transparent objects. - Yuanlin Hong; Junhong Chen; Yu Cheng; Yishi Han; Frank Van Reeth; Luc Claesen; Wenyin Liu (Frontiers Neurorobotics, 2022)

Structured Term Pruning for Computational Efficient Neural Networks Inference. - Kai Huang 002; Bowen Li 017; Siang Chen; Luc Claesen; Wei Xi; Junjian Chen; Xiaowen Jiang 001; Zhili Liu; Dongliang Xiong; Xiaolang Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Structured Dynamic Precision for Deep Neural Networks Quantization. - Kai Huang 002; Bowen Li 017; Dongliang Xiong; Haitian Jiang; Xiaowen Jiang 001; Xiaolang Yan; Luc Claesen; Dehong Liu; Junjian Chen; Zhili Liu (ACM Trans. Design Autom. Electr. Syst., 2023)

Feature Correlation Transformer for Estimating Ambiguous Optical Flow. - Guibiao Fang; Junhong Chen; Dayong Liang; Muhammad Asim 002; Frank Van Reeth; Luc Claesen; Zhenguo Yang; Wenyin Liu (Neural Process. Lett., 2023)

DistillGrasp: Integrating Features Correlation With Knowledge Distillation for Depth Completion of Transparent Objects. - Yiheng Huang; Junhong Chen; Nick Michiels; Muhammad Asim 002; Luc Claesen; Wenyin Liu (IEEE Robotics Autom. Lett., 2024)