Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. - Florent de Dinechin; Silviu-Ioan Filip; Martin Kumm; Luc Forget (ARITH, 2019)

Evaluating the Hardware Cost of the Posit Number System. - Yohann Uguen; Luc Forget; Florent de Dinechin (FPL, 2019)

A type-safe arbitrary precision arithmetic portability layer for HLS tools. - Luc Forget; Yohann Uguen; Florent de Dinechin; David Thomas 001 (HEART, 2019)

A single-source C++20 HLS flow for function evaluation on FPGA and beyond. - Luc Forget; Gauthier Harnisch; Ronan Keryell; Florent de Dinechin (HEART, 2022)

Lossless Differential Table Compression for Hardware Function Evaluation. - Maxime Christ; Luc Forget; Florent de Dinechin (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Description and compilation of ad-hoc arithmetic operators in the context of High-Level Synthesis. (Description et compilation d'opérateurs arithmétique ad-hoc dans un contexte de synthèse de haut niveau). - Luc Forget (2023)