To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters. - Luca Bertaccini; Luca Benini; Francesco Conti 001 (ASAP, 2021)

A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. - Thomas Benz; Luca Bertaccini; Florian Zaruba; Fabian Schuiki; Frank K. Gürkaynak; Luca Benini (ESSCIRC, 2021)

Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. - Luca Bertaccini; Matteo Perotti; Stefan Mach; Pasquale Davide Schiavone; Florian Zaruba; Luca Benini (ISCAS, 2021)

RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. - Matteo Perotti; Giuseppe Tagliavini; Stefan Mach; Luca Bertaccini; Luca Benini (SAMOS, 2021)

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores. - Luca Bertaccini; Gianna Paulin; Tim Fischer 001; Stefan Mach; Luca Benini (ARITH, 2022)

RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs. - Yvan Tortorella; Luca Bertaccini; Davide Rossi; Luca Benini; Francesco Conti 001 (DATE, 2022)

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. - Gianna Paulin; Matheus A. Cavalcante; Paul Scheffler; Luca Bertaccini; Yichao Zhang 003; Frank K. Gürkaynak; Luca Benini (ISVLSI, 2022)

ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays. - Mattia Sinigaglia; Luca Bertaccini; Luca Valente; Angelo Garofalo; Simone Benatti; Luca Benini; Francesco Conti 001; Davide Rossi (ISCAS, 2023)

Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays. - Mattia Sinigaglia; Luca Bertaccini; Luca Valente; Angelo Garofalo; Simone Benatti; Luca Benini; Francesco Conti 001; Davide Rossi (CoRR, 2023)

RedMule: A mixed-precision matrix-matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration. - Yvan Tortorella; Luca Bertaccini; Luca Benini; Davide Rossi; Francesco Conti 001 (Future Gener. Comput. Syst., 2023)

Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations. - Luca Bertaccini; Siyuan Shen; Torsten Hoefler; Luca Benini (ICCD, 2024)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform. - Viviane Potocnik; Luca Colagrande; Tim Fischer 001; Luca Bertaccini; Daniele Jahier Pagliari; Alessio Burrello; Luca Benini (CoRR, 2024)

MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products. - Luca Bertaccini; Gianna Paulin; Matheus A. Cavalcante; Tim Fischer 001; Stefan Mach; Luca Benini (IEEE Trans. Emerg. Top. Comput., 2024)

RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine. - Philip Wiese; Maurus Item; Luca Bertaccini; Yvan Tortorella; Angelo Garofalo; Luca Benini (CF (Companion), 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. - Mattia Sinigaglia; Amirhossein Kiamarzi; Marco Bertuletti; Luigi Ghionda; Mattia Orlandi; Riccardo Tedeschi; Aurora Di Giampietro; Yvan Tortorella; Luca Bertaccini; Simone Benatti; Giuseppe Tagliavini; Luca Benini; et al. (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)

MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products. - Gamze Islamoglu; Luca Bertaccini; Arpan Suravi Prasad; Francesco Conti 001; Angelo Garofalo; Luca Benini (CoRR, 2025)