Failure probability of SRAM-FPGA systems with Stochastic Activity Networks. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici (DDECS, 2011)

Failure Probability and Fault Observability of SRAM-FPGA Systems. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici (FPL, 2011)

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici; Luca Sterpone (DFT, 2012)

SEU-X: A SEu un-excitability prover for SRAM-FPGAs. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici (IOLTS, 2012)

Formal approaches to SEU testing in FPGAs. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici (AHS, 2013)

On-line testing of permanent radiation effects in reconfigurable systems. - Luca Cassano; Dario Cozzi; Sebastian Korf; Jens Hagemeyer; Mario Porrmann; Luca Sterpone (DATE, 2013)

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici; Luca Sterpone (ACM Great Lakes Symposium on VLSI, 2013)

Mitigation of Single Event Upsets in the control logic of a charge equalizer for Li-ion batteries. - Federico Baronti; Cinzia Bernardeschi; Luca Cassano; Andrea Domenici; Roberto Roncella; Roberto Saletti (IECON, 2013)

GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs. - Cinzia Bernardeschi; Luca Cassano; Mario G. C. A. Cimino; Andrea Domenici (J. Syst. Archit., 2013)

Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs. - Luca Cassano (2013)

Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations. - Daniel Cesarini; Luca Cassano; Alessio Fagioli 002; Marco Avvenuti (ES4CPS@DATE, 2014)

Machine learning-based techniques for incremental functional diagnosis: A comparative analysis. - Cristiana Bolchini; Luca Cassano (DFT, 2014)

Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems. - Domenico G. Sorrenti; Dario Cozzi; Sebastian Korf; Luca Cassano; Jens Hagemeyer; Mario Porrmann; Cinzia Bernardeschi (DFT, 2014)

An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems. - Luca Cassano; Dario Cozzi; Dirk Jungewelter; Sebastian Korf; Jens Hagemeyer; Mario Porrmann; Cinzia Bernardeschi (DTIS, 2014)

A novel adaptive fault tolerant flip-flop architecture based on TMR. - Luca Cassano; Alberto Bosio; Giorgio Di Natale (ETS, 2014)

Early assessment of SEU sensitivity through untestable fault identification. - Luca Cassano; Hipólito Guzmán-Miranda; Miguel A. Aguirre (IOLTS, 2014)

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs. - Luca Cassano (ITC, 2014)

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici; Luca Sterpone (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-Ion Batteries. - Federico Baronti; Cinzia Bernardeschi; Luca Cassano; Andrea Domenici; Roberto Roncella; Roberto Saletti (IEEE Trans. Ind. Informatics, 2014)

A configurable board-level adaptive incremental diagnosis technique based on decision trees. - Cristiana Bolchini; Luca Cassano (DFTS, 2015)

SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici (J. Comput. Sci. Technol., 2015)

An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards. - Cristiana Bolchini; Luca Cassano; Paolo Garza; Elisa Quintarelli; Fabio Salice (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis. - Cristiana Bolchini; Luca Cassano; Antonio Miele (DATE, 2016)

Adapting the Duty Cycle to Traffic Load in a Preamble Sampling MAC for WSNs: Formal Specification and Performance Evaluation. - Marco Avvenuti; Cinzia Bernardeschi; Luca Cassano; Alessio Vecchio (Ad Hoc Sens. Wirel. Networks, 2016)

UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs. - Cinzia Bernardeschi; Luca Cassano; Andrea Domenici; Luca Sterpone (Integr., 2016)

A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards. - Cristiana Bolchini; Luca Cassano (IEEE Trans. Computers, 2016)

A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis. - Cristiana Bolchini; Luca Cassano (IEEE Des. Test, 2017)

OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems. - Dario Cozzi; Sebastian Korf; Luca Cassano; Jens Hagemeyer; Andrea Domenici; Cinzia Bernardeschi; Luca Sterpone; Mario Porrmann (IEEE Trans. Emerg. Top. Comput., 2018)

A Smart Fault Detection Scheme for Reliable Image Processing Applications. - Matteo Biasielli; Cristiana Bolchini; Luca Cassano; Antonio Miele (DATE, 2019)

Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking. - Ana Lasheras; Ramon Canal; Eva Rodríguez; Luca Cassano (DFT, 2019)

HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems. - Cristiana Bolchini; Luca Cassano; Ivan Montalbano; Giampiero Repole; Andrea Zanetti; Giorgio Di Natale (IOLTS, 2019)

An Approximation-based Fault Detection Scheme for Image Processing Applications. - Matteo Biasielli; Luca Cassano; Antonio Miele (DATE, 2020)

Lightweight Fault Detection and Management for Image Restoration. - Cristiana Bolchini; Luca Cassano; Antonio Miele; Matteo Biasielli (DFT, 2020)

A Microprocessor Protection Architecture against Hardware Trojans in Memories. - Alperen Bolat; Luca Cassano; Pedro Reviriego; Oguz Ergin; Marco Ottavi (DTIS, 2020)

Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs. - Cristiana Bolchini; Luca Cassano; Andrea Mazzeo; Antonio Miele (IOLTS, 2020)

Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis. - Ana Lasheras; Ramon Canal; Eva Rodríguez; Luca Cassano (IOLTS, 2020)

A methodology for the design and deployment of distributed cyber-physical systems for smart environments. - Giacomo Tanganelli; Luca Cassano; Antonio Miele; Carlo Vallati (Future Gener. Comput. Syst., 2020)

A Neural Network Based Fault Management Scheme for Reliable Image Processing. - Matteo Biasielli; Cristiana Bolchini; Luca Cassano; Erdem Koyuncu; Antonio Miele (IEEE Trans. Computers, 2020)

Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications. - Cristiana Bolchini; Luca Cassano; Andrea Mazzeo; Antonio Miele (DFT, 2021)

A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses. - Alessandro Palumbo; Luca Cassano; Pedro Reviriego; Giuseppe Bianchi 001; Marco Ottavi (DFT, 2021)

On the Optimization of Behavioral Logic Locking for High-Level Synthesis. - Christian Pilato; Luca Collini; Luca Cassano; Donatella Sciuto; Siddharth Garg; Ramesh Karri (CoRR, 2021)

Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? - Cristiana Bolchini; Alberto Bosio; Luca Cassano; Bastien Deveautour; Giorgio Di Natale; Antonio Miele; Ian O'Connor; Elena-Ioana Vatajelu (DDECS, 2022)

On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors. - Luca Cassano; Elia Lazzeri; Nikita Litovchenko; Giorgio Di Natale (DDECS, 2022)

Selective Hardening of CNNs based on Layer Vulnerability Estimation. - Cristiana Bolchini; Luca Cassano; Antonio Miele; Alessandro Nazzari (DFT, 2022)

Is RISC-V ready for Space? A Security Perspective. - Luca Cassano; Stefano Di Mascio; Alessandro Palumbo; Alessandra Menicucci; Gianluca Furano; Giuseppe Bianchi 001; Marco Ottavi (DFT, 2022)

Design of Fault-Tolerant Distributed Cyber-Physical Systems for Smart Environments. - Luca Cassano; Antonio Miele; Francesco Mione; Nicola Tonellotto; Carlo Vallati (IEEE Embed. Syst. Lett., 2022)

DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN. - Luca Cassano; Mattia Iamundo; Tomas Antonio Lopez; Alessandro Nazzari; Giorgio Di Natale (J. Syst. Archit., 2022)

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer. - Alessandro Palumbo; Luca Cassano; Bruno Luzzi; José Alberto Hernández 001; Pedro Reviriego; Giuseppe Bianchi 001; Marco Ottavi (J. Syst. Archit., 2022)

Fault Impact Estimation for Lightweight Fault Detection in Image Filtering. - Cristiana Bolchini; Giacomo Boracchi; Luca Cassano; Antonio Miele; Diego Stucchi (IEEE Trans. Computers, 2022)

Approximation-Based Fault Tolerance in Image Processing Applications. - Matteo Biasielli; Cristiana Bolchini; Luca Cassano; Andrea Mazzeo; Antonio Miele (IEEE Trans. Emerg. Top. Comput., 2022)

A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures. - Antonio Miele; Henry Zárate; Luca Cassano; Cristiana Bolchini; Jorge Eduardo Ortiz Trivino (ACM Trans. Internet Things, 2022)

Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. - Kerem Arikan; Alessandro Palumbo; Luca Cassano; Pedro Reviriego; Salvatore Pontarelli; Giuseppe Bianchi 001; Oguz Ergin; Marco Ottavi (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications. - Cristiana Bolchini; Luca Cassano; Antonio Miele; Alessandro Nazzari; Dario Passarello (DFT, 2023)

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. - Alessandro Palumbo; Luca Cassano; Pedro Reviriego; Marco Ottavi (DFT, 2023)

Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses. - Alessandro Palumbo; Marco Ottavi; Luca Cassano (DFT, 2023)

Towards Dependable RISC-V Cores for Edge Computing Devices. - Pegdwende Romaric Nikiema; Alessandro Palumbo; Allan Aasma; Luca Cassano; Angeliki Kritikakou; Ari Kulmala; Jari Lukkarila; Marco Ottavi; Rafail Psiakis; Marcello Traiola (IOLTS, 2023)

Resilience of Deep Learning applications: a systematic survey of analysis and hardening techniques. - Cristiana Bolchini; Luca Cassano; Antonio Miele (CoRR, 2023)

Optimizing the Use of Behavioral Locking for High-Level Synthesis. - Christian Pilato; Luca Collini; Luca Cassano; Donatella Sciuto; Siddharth Garg; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Fast and Accurate Error Simulation for CNNs Against Soft Errors. - Cristiana Bolchini; Luca Cassano; Antonio Miele; Alessandro Toschi (IEEE Trans. Computers, 2023)

Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes. - Bruno Endres Forlin; Kuan-Hsun Chen; Nikolaos Alachiotis 001; Luca Cassano; Marco Ottavi (DATE, 2024)

Range Restriction to Harden CNNs Against Hardware Faults: A Broad Empirical Analysis. - Cristiana Bolchini; Luca Cassano; Antonio Miele; Dario Passarella (DFT, 2024)

An Experimental Comparison of RISC-V Processors: Performance, Power, Area and Security - Special Session Paper-. - Elia Lazzeri; Bruno E. Forlin; Gianluca Furano; Marco Ottavi; Luca Cassano (DFT, 2024)

Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. - Alessandro Veronesi; Alessandro Nazzari; Dario Passarello; Milos Krstic; Michele Favalli; Luca Cassano; Antonio Miele; Davide Bertozzi; Cristiana Bolchini (ETS, 2024)

Resilience of deep learning applications: A systematic literature review of analysis and hardening techniques. - Cristiana Bolchini; Luca Cassano; Antonio Miele (Comput. Sci. Rev., 2024)

S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors. - Elia Lazzeri; Matteo Colella; Gianluca Furano; Luca Cassano (DDECS, 2025)