SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers. - Paul Scheffler; Luca Colagrande; Luca Benini (DAC, 2024)

Optimizing Offload Performance in Heterogeneous MPSoCs. - Luca Colagrande; Luca Benini (DATE, 2024)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform. - Viviane Potocnik; Luca Colagrande; Tim Fischer 001; Luca Bertaccini; Daniele Jahier Pagliari; Alessio Burrello; Luca Benini (CoRR, 2024)

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors. - Luca Colagrande; Jayanth Jonnalagadda; Luca Benini (DATE, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

A Multicast-Capable AXI Crossbar for Many-core Machine Learning Accelerators. - Luca Colagrande; Luca Benini (CoRR, 2025)

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores. - Luca Colagrande; Luca Benini (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)

FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators. - Chi Zhang; Luca Colagrande; Renzo Andri; Thomas Benz; Gamze Islamoglu; Alessandro Nadalini; Francesco Conti 001; Yawei Li 001; Luca Benini (CoRR, 2025)

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration. - Luca Colagrande; Lorenzo Leone; Maximilian Coco; Andrei Deaconeasa; Luca Benini (CoRR, 2025)

Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization. - Luca Colagrande; Luca Benini (IEEE Trans. Parallel Distributed Syst., 2025)