Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices. - Andrea Silvagni; Stefano Zanardi; Alessandro Manstretta; Marco Scotti; Luca Crippa; Giancarlo Ragone; Giuseppe Fusillo; Giovanni Campardo; Osama Khouri; Marcello Stefanelli (ICECS, 2001)

The flash memory read path: building blocks and critical aspects. - Rino Micheloni; Luca Crippa; Miriam Sangalli; Giovanni Campardo (Proc. IEEE, 2003)

A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput. - Rino Micheloni; R. Ravasio; Alessia Marelli; E. Alice; V. Altieri; A. Bovino; Luca Crippa; E. Di Martino; L. D'Onofrio; A. Gambardella; E. Grillea; G. Guerra; et al. (ISSCC, 2006)

3D Charge Trap NAND Flash Memories. - Luca Crippa; Rino Micheloni (3D Flash Memories, 2016)

Advanced Architectures for 3D NAND Flash Memories with Vertical Channel. - Luca Crippa; Rino Micheloni (3D Flash Memories, 2016)

3D Stacked NAND Flash Memories. - Rino Micheloni; Luca Crippa (3D Flash Memories, 2016)

3D Floating Gate NAND Flash Memories. - Rino Micheloni; Luca Crippa (3D Flash Memories, 2016)

Architectural and Integration Options for 3D NAND Flash Memories. - Rino Micheloni; Luca Crippa; Cristian Zambelli; Piero Olivo (Comput., 2017)

Array Architectures for 3-D NAND Flash Memories. - Rino Micheloni; Seiichi Aritome; Luca Crippa (Proc. IEEE, 2017)

A Serverless Cloud Integration For Quantum Computing. - Michele Grossi; Luca Crippa; Antonello Aita; Giacomo Bartoli; Vito Sammarco; Eleonora Picca; N. Said; Filippo Tramonto; Federico Mattei (CoRR, 2021)

Leveraging Large-Scale TLC 3D NAND Flash Characterization to Investigate Early Lifetime Reliability of SSDs through Extreme Value Statistics. - Rino Micheloni; Luca Crippa; Alessia Marelli; Lorenzo Zuolo; Piero Olivo; Cristian Zambelli (IRPS, 2025)