A full-adder based reconfigurable architecture for fine grain applications: ADAPTO. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re (ICECS, 2008)

ADAPTO: full-adder based reconfigurable architecture for bit level operations. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re; Alberto Nannarelli (ISCAS, 2008)

Arithmetic/Logic Blocks for Fine-grained Reconfigurable Units. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re (ISCAS, 2009)

Speed-up of RISC Processor Computation using ADAPTO. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re (ISCAS, 2009)

VLSI implementation of reconfigurable cells for RFU in embedded processors. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Christian Lenci; Marco Re (ICECS, 2010)

Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re (WISES, 2010)

Fine-grain Reconfigurable Functional Unit for embedded processors. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re (ACSCC, 2011)

Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Ruby B. Lee (ACSCC, 2012)

Spiking neural networks based on LIF with latency: Simulation and synchronization effects. - Gian Carlo Cardarilli; Alessandro Cristini; Luca Di Nunzio; Marco Re; Mario Salerno; Gianluca Susi (ACSSC, 2013)

A Reconfigurable Functional Unit for Modular Operations. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Salvatore Pontarelli; Marco Re (ApplePies, 2013)

TDES cryptography algorithm acceleration using a reconfigurable functional unit. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re (ICECS, 2014)

A Wireless Sensor Node Based on Microbial Fuel Cell. - Simone Acciarito; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re (ApplePies, 2015)

Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. - A. Esposito; Andrea Lomuscio; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2016)

Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach. - Simone Acciarito; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Gaurav Mani Khanal; Marco Re (ApplePies, 2016)

ZnO-rGO Composite Thin Film Resistive Switching Device: Emulating Biological Synapse Behavior. - Gaurav Mani Khanal; Simone Acciarito; Gian Carlo Cardarilli; Abhishek Chakraborty; Luca Di Nunzio; Rocco Fazzolari; Alessandro Cristini; Gianluca Susi; Marco Re (ApplePies, 2016)

Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams. - Filippo Giuliani; Marco Ottavi; Gian Carlo Cardarilli; Marco Re; Luca Di Nunzio; Rocco Fazzolari; Antimo Bruno; Francesco Zuliani (DFT, 2016)

A Wireless Sensor Node for Acoustic Emission Non-destructive Testing. - Gian Carlo Cardarilli; Luca Di Nunzio; Federico Massimi; Rocco Fazzolari; Carlo De Petris; Giuseppe Augugliaro; Canio Mennuti (ApplePies, 2017)

FPGA Implementation of a Low-Power QRS Extractor. - Francesca Silvestri; Simone Acciarito; Gian Carlo Cardarilli; Gaurav Mani Khanal; Luca Di Nunzio; Rocco Fazzolari; Marco Re (ApplePies, 2017)

A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Luca Gerardi; Marco Re; Giovanni Campolo; Domenico Cascone (ISCAS, 2017)

Robust throughput boosting for low latency dynamic partial reconfiguration. - Alberto Nannarelli; Marco Re; Gian Carlo Cardarilli; Luca Di Nunzio; M. Spaziani Brunella; Rocco Fazzolari; F. Carbonari (SoCC, 2017)

Hardware design of LIF with Latency neuron model with memristive STDP synapses. - Simone Acciarito; Gian Carlo Cardarilli; Alessandro Cristini; Luca Di Nunzio; Rocco Fazzolari; Gaurav Mani Khanal; Marco Re; Gianluca Susi (Integr., 2017)

A Power Efficient Digital Front-End for Cognitive Radio Systems. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2018)

Efficient Ensemble Machine Learning Implementation on FPGA Using Partial Reconfiguration. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Francesca Silvestri; Sergio Spanò (ApplePies, 2018)

Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility. - Marco Ottavi; Dario Asciolla; Tiziano Fiorucci; Elena Grosso; Carla Marzullo; Alessandro Scaramella; Simone Stramaccioni; Alessia Zibecchi; Carla Andreani; Gian Carlo Cardarilli; Carlo Cazzaniga; Luca Di Nunzio; et al. (DTIS, 2018)

Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Dario Gelfusa; Marco Matta; Alberto Nannarelli; Marco Re; Lorenzo Simone; Sergio Spanò (SMACD, 2018)

Channel estimation for high speed unmanned aerial vehicle with STBC in MIMO radio links. - Amirhossein Fereidountabar; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari (Int. J. Comput. Vis. Robotics, 2018)

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2019)

Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Sergio Spanò (ApplePies, 2019)

Digital Signal Processing Accelerator for RISC-V. - L. Calicchia; V. Ciotoli; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ICECS, 2019)

A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. - Marco Matta; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Access, 2019)

An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. - Sergio Spanò; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Alberto Nannarelli; Marco Re (IEEE Access, 2019)

FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Alberto Nannarelli; Marco Re; Sergio Spanò (ACSSC, 2020)

An Action-Selection Policy Generator for Reinforcement Learning Hardware Accelerators. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Sergio Spanò (ApplePies, 2020)

N-Dimensional Approximation of Euclidean Distance. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

AW-SOM, an Algorithm for High-Speed Learning in Hardware Self-Organizing Maps. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

"MR Q-Learning" Algorithm for Efficient Hardware Implementations. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Dario Natale; Marco Re; Sergio Spanò (ACSCC, 2021)

A M-PSK Timing Recovery Loop Based on Q-Learning. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Matteo Guadagno; Marco Re; Sergio Spanò (ApplePies, 2021)

Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Riccardo La Cesa; Marco Re (SYSTEM, 2021)

A Parallel Hardware Implementation for 2-D Hierarchical Clustering Based on Fuzzy Logic. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Massimo Panella; Marco Re; Antonello Rosato; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

M-PSK Demodulator With Joint Carrier and Timing Recovery. - Daniele Giardino; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (ApplePies, 2022)

FPGA-Based Road Crack Detection Using Deep Learning. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (SYSINT, 2022)

An FPGA-based multi-agent Reinforcement Learning timing synchronizer. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Andrea Ricci; Sergio Spanò (Comput. Electr. Eng., 2022)

Sensing and Detection of Traffic Signs Using CNNs: An Assessment on Their Performance. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Hamed Famil Ghadakchi; Marco Re; Sergio Spanò (Sensors, 2022)

Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Massimo Petricca; Marco Re (IEEE Trans. Emerg. Top. Comput., 2022)

A Hardware-Oriented QAM Demodulation Method Driven by AW-SOM Machine Learning. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (ACSSC, 2023)

Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Riccardo La Cesa; Alberto Nannarelli; Marco Re (ACSSC, 2023)

A RISC-V Hardware Accelerator for Q-Learning Algorithm. - Damiano Angeloni; Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re; Sergio Spanò (ApplePies, 2023)

An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Alberto Nannarelli; Sergio Spanò (IEEE Access, 2023)

Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A RISC-V Hardware Accelerator for AW-SOM Machine Learning. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Riccardo La Cesa; Mariano Neroni; Simone Pace; Sergio Spanò (IEEECONF, 2024)

Onboard FPGA AI/ML Processing on Landsat-8 Satellite Images: A Case Study of Wildfires Detection. - Lorenzo Canese; Gian Carlo Cardarilli; Giuseppe D'Angelo; Luca Di Nunzio; Piero Gabellini; Riccardo La Cesa; Marco Re; Sergio Spanò (ApplePies, 2024)

Automatic Tunable Floating-Point Format Selection in a RISC-V Ecosystem. - Alberto Nannarelli; Marco Re; Gian Carlo Cardarilli; Luca Di Nunzio; Sergio Spanò (ApplePies, 2024)

Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey. - Stefano Bertazzoni; Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (IEEE Access, 2024)

A Novel Digital Equalizer Based on RF Sampling Beyond GHz. - Lorenzo Canese; Gian Carlo Cardarilli; Riccardo La Cesa; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Sergio Spanò (IEEE Access, 2024)

High efficiency hardware implementation of a ZP-OTFS modulator for next generation high-mobility wireless systems. - Riccardo La Cesa; Simone Acciarito; Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re; Sergio Spanò; Cristian Valenti (Comput. Electr. Eng., 2025)