Nanofabric power analysis: Biosequence alignment case study. - Stefano Frache; Luca Gaetano Amarù; Mariagrazia Graziano; Maurizio Zamboni (NANOARCH, 2011)

High Speed Architectures for Finding the First two Maximum/Minimum Values. - Luca Gaetano Amarù; Maurizio Martina; Guido Masera (IEEE Trans. Very Large Scale Integr. Syst., 2012)

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2013)

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DAC, 2013)

Towards structured ASICs using polarity-tunable Si nanowire transistors. - Pierre-Emmanuel Gaillardon; Michele De Marchi; Luca Gaetano Amarù; Shashikanth Bobba; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DAC, 2013)

Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2013)

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Shashikanth Bobba; Michele De Marchi; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DATE, 2013)

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET. - Ogun Turkyilmaz; Fabien Clermidy; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2013)

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Jian Zhang 067; Giovanni De Micheli (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Data compression via logic synthesis. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Andreas Burg 001; Giovanni De Micheli (ASP-DAC, 2014)

Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DAC, 2014)

An efficient manipulation package for Biconditional Binary Decision Diagrams. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2014)

Advanced system on a chip design based on controllable-polarity FETs. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Jian Zhang 067; Giovanni De Micheli (DATE, 2014)

Majority Logic Synthesis for Spin Wave Technology. - Odysseas Zografos; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Praveen Raghavan; Giovanni De Micheli (DSD, 2014)

A new basic logic structure for data-path computation (abstract only). - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Giovanni De Micheli (FPGA, 2014)

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Giovanni De Micheli (ISVLSI, 2014)

System-level assessment and area evaluation of Spin Wave logic circuits. - Odysseas Zografos; Praveen Raghavan; Luca Gaetano Amarù; Bart Soree; Rudy Lauwereins; Iuliana P. Radu; Diederik Verkest; Aaron Thean (NANOARCH, 2014)

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Multiple Independent Gate FETs: How many gates do we need? - Luca Gaetano Amarù; Gage Hills; Pierre-Emmanuel Gaillardon; Subhasish Mitra; Giovanni De Micheli (ASP-DAC, 2015)

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). - Pierre-Emmanuel Gaillardon; Gain Kim; Xifan Tang; Luca Gaetano Amarù; Giovanni De Micheli (FPGA, 2015)

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. - Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino; Luca Gaetano Amarù; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2015)

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams. - Anupam Chattopadhyay; Alessandro Littarru; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISMVL, 2015)

Exploiting Circuit Duality to Speed up SAT. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Alan Mishchenko; Maciej J. Ciesielski; Giovanni De Micheli (ISVLSI, 2015)

A fast pruning technique for low-power inexact Circuit design. - Johan Broc; Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Jaume Joven Murillo; Krishna V. Palem; Giovanni De Micheli (LASCAS, 2015)

NEM relay design with biconditional binary decision diagrams. - Winston Haaswijk; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (NANOARCH, 2015)

New Logic Synthesis as Nanotechnology Enabler. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Subhasish Mitra; Giovanni De Micheli (Proc. IEEE, 2015)

New Data Structures and Algorithms for Logic Synthesis and Verification. - Luca Gaetano Amarù (2015)

Majority-based synthesis for nanotechnologies. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2016)

An MIG-based compiler for programmable logic-in-memory architectures. - Mathias Soeken; Saeideh Shirinzadeh; Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Rolf Drechsler; Giovanni De Micheli (DAC, 2016)

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Robert Wille; Giovanni De Micheli (DATE, 2016)

The Programmable Logic-in-Memory (PLiM) computer. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Anne Siemon; Eike Linn; Rainer Waser; Anupam Chattopadhyay; Giovanni De Micheli (DATE, 2016)

Optimizing Majority-Inverter Graphs with functional hashing. - Mathias Soeken; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2016)

Digital, analog and RF design opportunities of three-independent-gate transistors. - Pierre-Emmanuel Gaillardon; Mehdi Hasan; Anirban Saha; Luca Gaetano Amarù; Ross Walker 001; Berardi Sensale Rodriguez (ISCAS, 2016)

Notes on Majority Boolean Algebra. - Anupam Chattopadhyay; Luca Gaetano Amarù; Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISMVL, 2016)

Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications. - Pierre-Emmanuel Gaillardon; Romain Magni; Luca Gaetano Amarù; Mehdi Hasan; Ross Walker 001; Berardi Sensale Rodriguez; Jean-Frédéric Christmann; Edith Beigné (LATS, 2016)

Inversion optimization in Majority-Inverter Graphs. - Eleonora Testa; Mathias Soeken; Odysseas Zografos; Luca Gaetano Amarù; Praveen Raghavan; Rudy Lauwereins; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (NANOARCH, 2016)

A Sound and Complete Axiomatization of Majority-n Logic. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Anupam Chattopadhyay; Giovanni De Micheli (IEEE Trans. Computers, 2016)

Majority-Inverter Graph: A New Paradigm for Logic Optimization. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Multi-level logic benchmarks: An exactness study. - Luca Gaetano Amarù; Mathias Soeken; Winston Haaswijk; Eleonora Testa; Patrick Vuillod; Jiong Luo; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2017)

A novel basis for logic rewriting. - Winston Haaswijk; Mathias Soeken; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2017)

Logic optimization and synthesis: Trends and directions in industry. - Luca Gaetano Amarù; Patrick Vuillod; Jiong Luo; Janet Olson (DATE, 2017)

Wave pipelining for majority-based beyond-CMOS technologies. - Odysseas Zografos; A. De Meester; Eleonora Testa; Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Luca Gaetano Amarù; Praveen Raghavan; Francky Catthoor; Rudy Lauwereins (DATE, 2017)

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. - Zhufei Chu; Xifan Tang; Mathias Soeken; Ana Petkovska; Grace Zgheib; Luca Gaetano Amarù; Yinshui Xia; Paolo Ienne; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2017)

Enabling exact delay synthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon; Janet Olson; Robert K. Brayton; Giovanni De Micheli (ICCAD, 2017)

Exact Synthesis of Majority-Inverter Graphs and Its Applications. - Mathias Soeken; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Canonical computation without canonical representation. - Alan Mishchenko; Robert K. Brayton; Ana Petkovska; Mathias Soeken; Luca G. Amarù; Antun Domic (DAC, 2018)

Improvements to boolean resynthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Janet Olson; Robert K. Brayton; Giovanni De Micheli (DATE, 2018)

Technology-aware logic synthesis for ReRAM based in-memory computing. - Debjyoti Bhattacharjee; Luca G. Amarù; Anupam Chattopadhyay (DATE, 2018)

Practical exact synthesis. - Mathias Soeken; Winston Haaswijk; Eleonora Testa; Alan Mishchenko; Luca Gaetano Amarù; Robert K. Brayton; Giovanni De Micheli (DATE, 2018)

Majority logic synthesis. - Luca G. Amarù; Eleonora Testa; Miguel Couceiro; Odysseas Zografos; Giovanni De Micheli; Mathias Soeken (ICCAD, 2018)

Integrated ESOP Refactoring for Industrial Designs. - Winston Haaswijk; Luca Gaetano Amarù; Patrick Vuillod; Jiong Luo; Mathias Soeken; Giovanni De Micheli (ICECS, 2018)

Size Optimization of MIGs with an Application to QCA and STMG Technologies. - Heinz Riener; Eleonora Testa; Luca G. Amarù; Mathias Soeken; Giovanni De Micheli (NANOARCH, 2018)

Scalable Generic Logic Synthesis: One Approach to Rule Them All. - Heinz Riener; Eleonora Testa; Winston Haaswijk; Alan Mishchenko; Luca G. Amarù; Giovanni De Micheli; Mathias Soeken (DAC, 2019)

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications. - Eleonora Testa; Mathias Soeken; Luca G. Amarù; Giovanni De Micheli (DAC, 2019)

Scalable Boolean Methods in a Modern Synthesis Flow. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Jiong Luo; Christopher Casares; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2019)

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. - Walter Lau Neto; Max Austin; Scott Temple; Luca G. Amarù; Xifan Tang; Pierre-Emmanuel Gaillardon (ICCAD, 2019)

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. - Walter Lau Neto; Xifan Tang; Max Austin; Luca G. Amarù; Pierre-Emmanuel Gaillardon (ISVLSI, 2019)

Logic Optimization of Majority-Inverter Graphs. - Heinz Riener; Eleonora Testa; Winston Haaswijk; Alan Mishchenko; Luca G. Amarù; Giovanni De Micheli; Mathias Soeken (MBMV, 2019)

Logic Synthesis for Established and Emerging Computing. - Eleonora Testa; Mathias Soeken; Luca Gaetano Amarù; Giovanni De Micheli (Proc. IEEE, 2019)

Mapping Monotone Boolean Functions into Majority. - Eleonora Testa; Mathias Soeken; Luca Gaetano Amarù; Winston Haaswijk; Giovanni De Micheli (IEEE Trans. Computers, 2019)

SAT-Sweeping Enhanced for Logic Synthesis. - Luca G. Amarù; Felipe S. Marranghello; Eleonora Testa; Christopher Casares; Vinicius N. Possani; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2020)

A Scalable Mixed Synthesis Framework for Heterogeneous Networks. - Max Austin; Scott Temple; Walter Lau Neto; Luca G. Amarù; Xifan Tang; Pierre-Emmanuel Gaillardon (DATE, 2020)

Extending Boolean Methods for Scalable Logic Synthesis. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Access, 2020)

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. - Eleonora Testa; Mathias Soeken; Heinz Riener; Luca G. Amarù; Giovanni De Micheli (IACR Cryptol. ePrint Arch., 2020)

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. - Walter Lau Neto; Matheus Trevisan Moreira; Luca G. Amarù; Cunxi Yu; Pierre-Emmanuel Gaillardon (ASP-DAC, 2021)

LUT-Based Optimization For ASIC Design Flow. - Luca Gaetano Amarù; Vinicius N. Possani; Eleonora Testa; Felipe S. Marranghello; Christopher Casares; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2021)

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. - Walter Lau Neto; Matheus T. Moreira; Yingjie Li; Luca G. Amarù; Cunxi Yu; Pierre-Emmanuel Gaillardon (DAC, 2021)

Deep Integration of Circuit Simulator and SAT Solver. - He-Teng Zhang; Jie-Hong R. Jiang; Luca G. Amarù; Alan Mishchenko; Robert K. Brayton (DAC, 2021)

Improving LUT-based optimization for ASICs. - Walter Lau Neto; Luca G. Amarù; Vinicius Possani; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon (DAC, 2022)

Majority-based Design Flow for AQFP Superconducting Family. - Giulia Meuli; Vinicius N. Possani; Rajinder Singh; Siang-Yun Lee; Alessandro Tempia Calvino; Dewmini Sudara Marakkalage; Patrick Vuillod; Luca G. Amarù; Scott Chase; Jamil Kawa; Giovanni De Micheli (DATE, 2022)

Scalable Sequential Optimization Under Observability Don't Cares. - Dewmini Sudara Marakkalage; Eleonora Testa; Walter Lau Neto; Alan Mishchenko; Giovanni De Micheli; Luca G. Amarù (DATE, 2024)