Luca G. Amarù

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Deep Integration of Circuit Simulator and SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

LUT-Based Optimization For ASIC Design Flow.

[BibT_eX]

[DOI]

Vinicius N. Possani

Eleonora Testa

Felipe S. Marranghello

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization.

[BibT_eX]

[DOI]

Walter Lau Neto

Matheus Trevisan Moreira

Luca G. Amarù

Cunxi Yu

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Extending Boolean Methods for Scalable Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Access, 2020

A Scalable Mixed Synthesis Framework for Heterogeneous Networks.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

SAT-Sweeping Enhanced for Logic Synthesis.

[BibT_eX]

[DOI]

Luca G. Amarù

Felipe S. Marranghello

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Mapping Monotone Boolean Functions into Majority.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Logic Synthesis for Established and Emerging Computing.

[BibT_eX]

[DOI]

Proc. IEEE, 2019

Logic Optimization of Majority-Inverter Graphs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Scalable Boolean Methods in a Modern Synthesis Flow.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Size Optimization of MIGs with an Application to QCA and STMG Technologies.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Integrated ESOP Refactoring for Industrial Designs.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Majority logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Practical exact synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Technology-aware logic synthesis for ReRAM based in-memory computing.

[BibT_eX]

[DOI]

Debjyoti Bhattacharjee

Luca G. Amarù

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improvements to boolean resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Canonical computation without canonical representation.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Exact Synthesis of Majority-Inverter Graphs and Its Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Enabling exact delay synthesis.

[BibT_eX]

[DOI]

Janet Olson

Robert K. Brayton

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Wave pipelining for majority-based beyond-CMOS technologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Logic optimization and synthesis: Trends and directions in industry.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A novel basis for logic rewriting.

[BibT_eX]

[DOI]

Winston Haaswijk

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Multi-level logic benchmarks: An exactness study.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Majority-Inverter Graph: A New Paradigm for Logic Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Sound and Complete Axiomatization of Majority-n Logic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Inversion optimization in Majority-Inverter Graphs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications.

[BibT_eX]

[DOI]

Berardi Sensale Rodriguez

Jean-Frédéric Christmann

Edith Beigné

Proceedings of the 17th Latin-American Test Symposium, 2016

Notes on Majority Boolean Algebra.

[BibT_eX]

[DOI]

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Digital, analog and RF design opportunities of three-independent-gate transistors.

[BibT_eX]

[DOI]

Berardi Sensale Rodriguez

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Optimizing Majority-Inverter Graphs with functional hashing.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The Programmable Logic-in-Memory (PLiM) computer.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking.

[BibT_eX]

[DOI]

Robert Wille

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An MIG-based compiler for programmable logic-in-memory architectures.

[BibT_eX]

[DOI]

Saeideh Shirinzadeh

Rolf Drechsler

Proceedings of the 53rd Annual Design Automation Conference, 2016

Majority-based synthesis for nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

New Data Structures and Algorithms for Logic Synthesis and Verification.

[BibT_eX]

[DOI]

PhD thesis, 2015

New Logic Synthesis as Nanotechnology Enabler.

[BibT_eX]

[DOI]

Subhasish Mitra

Proc. IEEE, 2015

NEM relay design with biconditional binary decision diagrams.

[BibT_eX]

[DOI]

Winston Haaswijk

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A fast pruning technique for low-power inexact Circuit design.

[BibT_eX]

[DOI]

Johan Broc

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Exploiting Circuit Duality to Speed up SAT.

[BibT_eX]

[DOI]

Alan Mishchenko

Maciej J. Ciesielski

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams.

[BibT_eX]

[DOI]

Alessandro Littarru

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Multiple Independent Gate FETs: How many gates do we need?

[BibT_eX]

[DOI]

Gage Hills

Subhasish Mitra

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

System-level assessment and area evaluation of Spin Wave logic circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A new basic logic structure for data-path computation (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Majority Logic Synthesis for Spin Wave Technology.

[BibT_eX]

[DOI]

Odysseas Zografos

Praveen Raghavan

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Advanced system on a chip design based on controllable-polarity FETs.

[BibT_eX]

[DOI]

Jian Zhang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An efficient manipulation package for Biconditional Binary Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Data compression via logic synthesis.

[BibT_eX]

[DOI]

Andreas Burg

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors.

[BibT_eX]

[DOI]

Jian Zhang

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET.

[BibT_eX]

[DOI]

Ogun Turkyilmaz

Fabien Clermidy

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Towards structured ASICs using polarity-tunable Si nanowire transistors.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

High Speed Architectures for Finding the First two Maximum/Minimum Values.

[BibT_eX]

[DOI]