Artificial Neural Networks for Motion Emulation in Virtual Environments. - Y. Bellan; Mario Costa; Giancarlo Ferrigno; Fabrizio Lombardi; Luca Macchiarulo; Alfonso Montuori; Eros Pasero; Camilla Rigotti (CAPTECH, 1998)

Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. - Luca Macchiarulo; Pierluigi Civera (ISMVL, 1998)

Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. - Luca Macchiarulo; Pierluigi Civera (VLSI Design, 1999)

Wave-steering one-hot encoded FSMs. - Luca Macchiarulo; Malgorzata Marek-Sadowska (DAC, 2000)

Wave Steered FSMs. - Luca Macchiarulo; Shih-Ming Shu; Malgorzata Marek-Sadowska (DATE, 2000)

A novel high throughput reconfigurable FPGA architecture. - Amit Singh 001; Luca Macchiarulo; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (FPGA, 2000)

A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'. - Elena Dubrova; Luca Macchiarulo (IEEE Trans. Computers, 2000)

FPGA-Based Fault Injection for Microprocessor Systems. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (Asian Test Symposium, 2001)

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. - Luca Benini; Luca Macchiarulo; Alberto Macii; Enrico Macii; Massimo Poncino (DAC, 2001)

On-the-fly layout generation for PTL macrocells. - Luca Macchiarulo; Luca Benini; Enrico Macii (DATE, 2001)

Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DFT, 2001)

FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (FPL, 2001)

Exploiting FPGA for Accelerating Fault Injection Experiments. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (IOLTW, 2001)

Low-energy for deep-submicron address buses. - Luca Macchiarulo; Enrico Macii; Massimo Poncino (ISLPED, 2001)

Wire Placement for Crosstalk Energy Minimization in Address Buses. - Luca Macchiarulo; Enrico Macii; Massimo Poncino (DATE, 2002)

A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. - Pierluigi Civera; Luca Macchiarulo; Massimo Violante (DFT, 2002)

Enhanced clustered voltage scaling for low power. - Monica Donno; Luca Macchiarulo; Alberto Macii; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2002)

An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (J. Electron. Test., 2002)

Layout-driven memory synthesis for embedded systems-on-chip. - Luca Benini; Luca Macchiarulo; Alberto Macii; Massimo Poncino (IEEE Trans. Very Large Scale Integr. Syst., 2002)

New techniques for efficiently assessing reliability of SOCs. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (Microelectron. J., 2003)

PITIA: an FPGA for throughput-intensive applications. - Amit Singh 001; Arindam Mukherjee 001; Luca Macchiarulo; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A new approach to latency insensitive design. - Mario R. Casu; Luca Macchiarulo (DAC, 2004)

Issues in Implementing Latency Insensitive Protocols. - Mario R. Casu; Luca Macchiarulo (DATE, 2004)

A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. - Luca Macchiarulo; Consolato F. Caccamo; Davide Pandini (ACM Great Lakes Symposium on VLSI, 2004)

On-Chip Transparent Wire Pipelining. - Mario R. Casu; Luca Macchiarulo (ICCD, 2004)

Floorplanning for throughput. - Mario R. Casu; Luca Macchiarulo (ISPD, 2004)

Pipelining Sequential Circuits with Wave Steering. - Luca Macchiarulo; Shih-Min Shu; Malgorzata Marek-Sadowska (IEEE Trans. Computers, 2004)

A New System Design Methodology for Wire Pipelined SoC. - Mario R. Casu; Luca Macchiarulo (DATE, 2005)

Floorplan assisted data rate enhancement through wire pipelining: a real assessment. - Mario R. Casu; Luca Macchiarulo (ISPD, 2005)

Throughput-driven floorplanning with wire pipelining. - Mario R. Casu; Luca Macchiarulo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Using Existing Digital Tools for Efficient Metabolic Pathway Simulations. - Luca Macchiarulo (EMBC, 2006)

Fully-Integrated Heart Rate Variability Monitoring System with an Efficient Memory. - Xiaoyue Wang; Mingqi Chen; Luca Macchiarulo; Olga Boric-Lubecke (EMBC, 2006)

Implementation analysis of NoC: a MPSoC trace-driven approach. - Sergio Tota; Mario R. Casu; Luca Macchiarulo (ACM Great Lakes Symposium on VLSI, 2006)

Floorplanning With Wire Pipelining in Adaptive Communication Channels. - Mario R. Casu; Luca Macchiarulo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Adaptive Latency-Insensitive Protocols. - Mario R. Casu; Luca Macchiarulo (IEEE Des. Test Comput., 2007)

Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis. - Mario R. Casu; Luca Macchiarulo (FMGALS@DATE, 2009)

A Case Study for NoC-Based Homogeneous MPSoC Architectures. - Sergio Tota; Mario R. Casu; Massimo Ruo Roch; Luca Macchiarulo; Maurizio Zamboni (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance. - Xin Gao; Luca Macchiarulo (DATE, 2010)

Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC. - Wansuree Massagram; Noah Hafner; Mingqi Chen; Luca Macchiarulo; Victor Lubecke; Olga Boric-Lubecke (IEEE Trans. Biomed. Circuits Syst., 2010)

A jumper insertion algorithm under antenna ratio and timing constraints. - Xin Gao; Luca Macchiarulo (ICCAD, 2011)