A system level IP integration methodology for fast SOC design. - Massimo Bocchi; Claudio Brunelli; Claudia De Bartolomeis; Luca Magagni; Fabio Campi (SoC, 2003)

A 0.14mW/Gbps high-density capacitive interface for 3D system integration. - Alberto Fazzi; Luca Magagni; Mauro Mirandola; Roberto Canegallo; Stefan Schmitz; Roberto Guerrieri (CICC, 2005)

Electrical measurement of alignment for 3D stacked chips. - Roberto Canegallo; Mauro Mirandola; Alberto Fazzi; Luca Magagni; Roberto Guerrieri; Karin Kaschlun (ESSCIRC, 2005)

Yield prediction for 3D capacitive interconnections. - Alberto Fazzi; Luca Magagni; Mario de Dominicis; Paolo Zoffoli; Roberto Canegallo; Pier Luigi Rolandi; Alberto L. Sangiovanni-Vincentelli; Roberto Guerrieri (ICCAD, 2006)

3D Capacitive Interconnections for High Speed Interchip Communication. - Roberto Canegallo; Alberto Fazzi; Luca Ciccarelli; Luca Magagni; Federico Natali; Pier Luigi Rolandi; Erik Jung; Léa Di Cioccio; Roberto Guerrieri (CICC, 2007)

3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities. - Alberto Fazzi; Roberto Canegallo; Luca Ciccarelli; Luca Magagni; Federico Natali; Erik Jung; Pier Luigi Rolandi; Roberto Guerrieri (ISSCC, 2007)

3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly. - Alberto Fazzi; Luca Magagni; Mauro Mirandola; Barbara Charlet; Léa Di Cioccio; Erik Jung; Roberto Canegallo; Roberto Guerrieri (IEEE J. Solid State Circuits, 2007)

3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities. - Alberto Fazzi; Roberto Canegallo; Luca Ciccarelli; Luca Magagni; Federico Natali; Erik Jung; Pier Luigi Rolandi; Roberto Guerrieri (IEEE J. Solid State Circuits, 2008)