Data Recovery and Retiming for the Fully Buffered DIMM 4.8Gb/s Serial Links. - Hamid Partovi; Wolfgang Walthes; Luca Ravezzi; Paul Lindt; Sivaraman Chokkalingam; Karthik Gopalakrishnan; Andreas Blum; Otto Schumacher; Claudio Andreotti; Michael Bruennert; Bruno Celli-Urbani; Dirk Friebe; et al. (ISSCC, 2006)

Single-ended transceiver design techniques for 5.33Gb/s graphics applications. - Hamid Partovi; Karthik Gopalakrishnan; Luca Ravezzi; Russell Homer; Otto Schumacher; Reinhold Unterricker; Werner Kederer (ISSCC, 2009)

A 3-stage Pseudo Single-phase Flip-flop family. - Hamid Partovi; Alfred Yeung; Luca Ravezzi; Mark Horowitz (VLSIC, 2012)

Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC. - Luca Ravezzi; Hamid Partovi; Dong Wang; C. Wang; Ronen Cohen; Matt Ashcraft; Alfred Yeung; Qawi Harvard; Russell Homer; John Ngai; Greg Favor (ESSCIRC, 2014)

5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology. - Alfred Yeung; Hamid Partovi; Qawi Harvard; Luca Ravezzi; John Ngai; Russell Homer; M. Ashcraft; Greg Favor (ISSCC, 2014)

Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC. - Luca Ravezzi; Hamid Partovi (IEEE J. Solid State Circuits, 2015)

Up-Conversion of Clock Phase Noise in Plesiochronous Data Links. - Luca Ravezzi (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Failure in Ring Oscillators With Capacitive Load. - Luca Ravezzi (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)