Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC. - Lucas A. Tambara; Fernanda Lima Kastensmidt; Paolo Rech; Tiago R. Balen; Marcelo Lubaszewski (ISVLSI, 2013)

Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs. - Lucas A. Tambara; Fernanda Lima Kastensmidt; Paolo Rech; Christopher Frost 002 (DFT, 2014)

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects. - Lucas A. Tambara; Jorge L. Tonfat; Ricardo Reis 001; Fernanda Lima Kastensmidt; Evaldo Carlos Fonseca Pereira; Rafael Galhardo Vaz; Odair Lelis Goncalez (LATW, 2014)

Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity. - Giovanni Bruni; Paolo Rech; Lucas A. Tambara; Gabriel L. Nazar; Fernanda Gusmão de Lima Kastensmidt; Ricardo Reis 001; Alessandro Paccagnella (VLSI-SoC, 2014)

Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects. - Lucas A. Tambara; Felipe Almeida; Paolo Rech; Fernanda Lima Kastensmidt; Giovanni Bruni; Christopher Frost 002 (ARC, 2015)

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments. - Jimmy Tarrillo; Jorge L. Tonfat; Lucas A. Tambara; Fernanda Lima Kastensmidt; Ricardo Reis 001 (LATS, 2015)

Exploring design diversity redundancy to improve resilience in mixed-signal systems. - Cristiano P. Chenet; Lucas A. Tambara; Gabriel de M. Borges; Fernanda Lima Kastensmidt; Marcelo Soares Lubaszewski; Tiago R. Balen (Microelectron. Reliab., 2015)

Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors. - Jorge L. Tonfat; Lucas A. Tambara; André Flores dos Santos; Fernanda Gusmão de Lima Kastensmidt (ARC, 2016)

Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC. - Ádria Barros de Oliveira; Lucas Antunes Tambara; Fernanda Lima Kastensmidt (ARC, 2017)

Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. - André Flores dos Santos; Lucas Antunes Tambara; Fabio Benevenuti; Jorge L. Tonfat; Fernanda Lima Kastensmidt (ARC, 2017)

Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors. - Ádria Barros de Oliveira; Lucas Antunes Tambara; Fernanda Lima Kastensmidt (LASCAS, 2017)

Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA. - André Flores dos Santos; Lucas Antunes Tambara; Fernanda Lima Kastensmidt (LASCAS, 2017)

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs. - Jorge L. Tonfat; Lucas A. Tambara; André Santos; Fernanda Lima Kastensmidt (Microprocess. Microsystems, 2017)

Analyzing the impact of radiation-induced failures in flash-based APSoC with and without fault tolerance techniques at CERN environment. - Lucas A. Tambara; Eduardo Chielle; Fernanda Lima Kastensmidt; Georgios Tsiligiannis; Salvatore Danzeca; Markus Brugger; A. Masi (Microelectron. Reliab., 2017)

Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission. - Fabio Benevenuti; Eduardo Chielle; Jorge L. Tonfat; Lucas A. Tambara; Fernanda Lima Kastensmidt; Carlos Alberto Zaffari; João Baptista dos Santos Martins; Otávio Santos Cupertino Durão (IPDPS Workshops, 2019)

Notched gate MOSFET for capacitance reduction in RF SOI technology. - Lucas Antunes Tambara; Pascal Masson; Julien Amouroux; Stéphane Monfray; Julien Dura; Frederic Gianesello; Julien Babic; Romain Debroucke; Loic Welter; Siddhartha Dhar; Bernadette Gros; Clement Charbuillet; et al. (DTTIS, 2023)

MOSFET electron mobility enhancement using source/drain recess. - Lucas Antunes Tambara; Paul Devoge; Pascal Masson; Julien Amouroux; Julien Dura; C. Rivero; Franck Julien (DTTIS, 2024)