Task parallel programming model + hardware acceleration = performance advantage. - Tamer Dallou; Divino Cesar Soares Lucas; Guido Araujo; Lucas Morais; Eduardo Ferreira Barbosa; Michael Frank 008; Richard Bagley; Raj Sayana (Hot Chips Symposium, 2016)

Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor. - Lucas Morais; Vitor Silva; Alfredo Goldman; Carlos Álvarez 001; Jaume Bosch; Michael Frank 008; Guido Araujo (MICRO, 2019)

Algorithms for Freight Train Scheduling. - Lucas Morais; Rodrigo Gonçalves; Alexandre Tazoniero; Fernando A. C. Gomide (IJCCI, 2022)

The TEXTAROSSA Project: Cool all the Way Down to the Hardware. - Antonio Filgueras; Giovanni Agosta; Marco Aldinucci; Carlos Álvarez 001; Pasqua D'Ambra; Massimo Bernaschi; Andrea Biagioni; Daniele Cattaneo 002; Alessandro Celestini; Massimo Celino; Carlotta Chiarini; Francesca Lo Cicero; et al. (DSD, 2024)

Enabling HW-Based Task Scheduling in Large Multicore Architectures. - Lucas Morais; Carlos Álvarez 001; Daniel Jiménez-González; Juan Miguel De Haro Ruiz; Guido Araujo; Michael Frank 008; Alfredo Goldman; Xavier Martorell (IEEE Trans. Computers, 2024)