Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis. - Ludovic Jacomme; Frédéric Pétrot; Rajesh K. Bawa (EUROMICRO, 1998)

Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. - Ludovic Jacomme; Frédéric Pétrot; Rajesh K. Bawa (VLSI Design, 1999)