Stochastic Target Problems with Controlled Loss in Jump Diffusion Models. - Ludovic Moreau (SIAM J. Control. Optim., 2011)

Hedging Under an Expected Loss Constraint with Small Transaction Costs. - Bruno Bouchard 002; Ludovic Moreau; H. Mete Soner (SIAM J. Financial Math., 2016)

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. - Thomas Haine; Quoc-Khoi Nguyen; François Stas; Ludovic Moreau; Denis Flandre; David Bol (ESSCIRC, 2017)

On a Class of Path-Dependent Singular Stochastic Control Problems. - Romuald Elie; Ludovic Moreau; Dylan Possamaï (SIAM J. Control. Optim., 2018)

A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. - Ludovic Moreau; Rémi Dekimpe; David Bol (ISCAS, 2019)

A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. - David Bol; Maxime Schramme; Ludovic Moreau; Thomas Haine; Pengcheng Xu 002; Charlotte Frenkel; Remi Dekimpe; François Stas; Denis Flandre (ISSCC, 2019)

A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection. - Martin Lefebvre 002; Ludovic Moreau; Rémi Dekimpe; David Bol (ISSCC, 2021)

SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. - Rémi Dekimpe; Maxime Schramme; Martin Lefebvre 002; Adrian Kneip; Roghayeh Saeidi; Mathieu Xhonneux; Ludovic Moreau; Marco Gonzalez; Thibault Pirson; David Bol (VLSI Circuits, 2021)

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. - David Bol; Maxime Schramme; Ludovic Moreau; Pengcheng Xu 002; Rémi Dekimpe; Roghayeh Saeidi; Thomas Haine; Charlotte Frenkel; Denis Flandre (IEEE J. Solid State Circuits, 2021)