Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. - Nacer-Eddine Zergainoh; Amer Baghdadi; Ludovic Tambour; Damien Lyonnard; Lovic Gauthier; Ahmed Amine Jerraya (DIPES, 2000)

An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells. - Ludovic Tambour; Nacer-Eddine Zergainoh; Pascal Urard; Henri Michel; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2003)

Méthodes de correction de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP : fondement théorique et implémentation. - Nacer-Eddine Zergainoh; Ludovic Tambour; Henri Michel; Ahmed Amine Jerraya (Tech. Sci. Informatiques, 2005)

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems. - Nacer-Eddine Zergainoh; Ludovic Tambour; Pascal Urard; Ahmed Amine Jerraya (EURASIP J. Adv. Signal Process., 2006)

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation. - Nacer-Eddine Zergainoh; Ludovic Tambour; Ahmed Amine Jerraya (IEEE Trans. Very Large Scale Integr. Syst., 2006)