Design and Implementation of a RISC V Processor on FPGA. - Ludovico Poli; Sangeet Saha; Xiaojun Zhai; Klaus D. McDonald-Maier (MSN, 2021)

Anomaly Behaviour tracing of CHERI-RISC V using Hardware-Software Co-design. - Michal Borowski; Chandrajit Pal; Sangeet Saha; Ludovico Poli; Xiaojun Zhai; Klaus D. McDonald-Maier (NEWCAS, 2023)