A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. - Luigi Blasi; Francesco Vigli; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2019)

Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. - Marcello Barbirotta; Antonio Mastrandrea; Francesco Menichelli; Francesco Vigli; Luigi Blasi; Abdallah Cheikh; Stefano Sordillo; Fabio Di Gennaro; Mauro Olivieri (DFT, 2020)