On leakage current temperature characterization using sub-pico-ampere circuit techniques. - Bernabé Linares-Barranco; Teresa Serrano-Gotarredona; Rafael Serrano-Gotarredona; Luis A. Camuñas (ISCAS (1), 2004)

The Stochastic I-Pot: A Circuit Block for Programming Bias Currents. - Rafael Serrano-Gotarredona; Luis A. Camuñas-Mesa; Teresa Serrano-Gotarredona; Juan A. Leñero-Bardallo; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Fully digital AER convolution chip for vision processing. - Luis A. Camuñas-Mesa; Antonio Acosta-Jimenez; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2008)

CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking. - Rafael Serrano-Gotarredona; Matthias Oster; Patrick Lichtsteiner; Alejandro Linares-Barranco; Rafael Paz-Vicente; Francisco Gomez-Rodriguez; Luis A. Camuñas-Mesa; Raphael Berner; Manuel Rivas Pérez; Tobi Delbruck; Shih-Chii Liu; Rodney J. Douglas; et al. (IEEE Trans. Neural Networks, 2009)

Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware. - Luis A. Camuñas-Mesa; José Antonio Pérez-Carrasco; Carlos Zamarreño-Ramos; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IJCNN, 2010)

On scalable spiking convnet hardware for cortex-like visual sensory processing systems. - Luis A. Camuñas-Mesa; José Antonio Pérez-Carrasco; Carlos Zamarreño-Ramos; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2010)

Fast vision through frameless event-based sensing and convolutional processing: application to texture recognition. - José Antonio Pérez-Carrasco; Begoña Acha; Carmen Serrano; Luis A. Camuñas-Mesa; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE Trans. Neural Networks, 2010)

A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput. - Luis A. Camuñas-Mesa; Antonio Acosta-Jimenez; Carlos Zamarreño-Ramos; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors. - Luis A. Camuñas-Mesa; Carlos Zamarreño-Ramos; Alejandro Linares-Barranco; Antonio Acosta-Jimenez; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE J. Solid State Circuits, 2012)

A Detailed and Fast Model of Extracellular Recordings. - Luis A. Camuñas-Mesa; Rodrigo Quian Quiroga (Neural Comput., 2013)

Live demonstration: Event-driven sensing and processing for high-speed robotic vision. - Luis A. Camuñas-Mesa; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (BioCAS, 2014)

Event-driven sensing and processing for high-speed robotic vision. - Luis A. Camuñas-Mesa; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (BioCAS, 2014)

Event-driven stereo vision with orientation filters. - Luis A. Camuñas-Mesa; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco; Sio-Hoi Ieng; Ryad Benosman (ISCAS, 2014)

Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA. - Luis A. Camuñas-Mesa; Y. Domínguez-Cordero; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2018)

Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion. - Luis A. Camuñas-Mesa; Teresa Serrano-Gotarredona; Sio-Hoi Ieng; Ryad Benosman; Bernabé Linares-Barranco (IEEE Trans. Neural Networks Learn. Syst., 2018)

Low-power hardware implementation of SNN with decision block for recognition tasks. - Luis A. Camuñas-Mesa; Bernabé Linares-Barranco; Teresa Serrano-Gotarredona (ICECS, 2019)

Self-Testing Analog Spiking Neuron Circuit. - Sarah A. El-Sayed; Luis A. Camuñas-Mesa; Bernabé Linares-Barranco; Haralampos-G. D. Stratigopoulos (SMACD, 2019)

Implementation of a tunable spiking neuron for STDP with memristors in FDSOI 28nm. - Luis A. Camuñas-Mesa; Bernabé Linares-Barranco; Teresa Serrano-Gotarredona (AICAS, 2020)

Using Neural Networks for Optimum band selection in Cognitive-Radio Systems. - Virginia Zúñiga-González; Luis A. Camuñas-Mesa; Bernabé Linares-Barranco; Teresa Serrano-Gotarredona; José M. de la Rosa 001 (ICECS, 2020)

Spiking Neuron Hardware-Level Fault Modeling. - Sarah A. El-Sayed; Theofilos Spyrou; Antonios Pavlidis; Engin Afacan; Luis A. Camuñas-Mesa; Bernabé Linares-Barranco; Haralampos-G. D. Stratigopoulos (IOLTS, 2020)

Lessons Learned the Hard Way. - Tobi Delbruck; Ibrahim Abe M. Elfadel; Shahzad Muzaffar; Germain Haessig; Bo Wang 012; Amine Bermak; Rui Graca; Luis A. Camuñas-Mesa; Bathiya Senevirathna; Pamela Abshire; Bernabé Linares-Barranco; Saeed Afshar; et al. (ISCAS, 2020)

Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar. - Charanraj Mohan; Luis A. Camuñas-Mesa; Elisa Vianello; Carlo Reita; José M. de la Rosa 001; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2020)

Low Order Wideband Multiplierless Comb Compensator. - Gordana Jovanovic-Dolecek; Luis A. Camuñas-Mesa; José M. de la Rosa 001 (MWSCAS, 2020)

Neuron Fault Tolerance in Spiking Neural Networks. - Theofilos Spyrou; Sarah A. El-Sayed; Engin Afacan; Luis A. Camuñas-Mesa; Bernabé Linares-Barranco; Haralampos-G. Stratigopoulos (DATE, 2021)

Cognitive Radio Circuits and Systems - Application to Digitizers. - Hassan Aboushady; Alhassan Sayed; Luis A. Camuñas-Mesa; José M. de la Rosa 001 (ISCAS, 2021)

Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices. - C. Mohan 005; Luis A. Camuñas-Mesa; José M. de la Rosa 001; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2021)

Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration. - Charanraj Mohan; Luis A. Camuñas-Mesa; José M. de la Rosa 001; Elisa Vianello; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE Access, 2021)

Reliability Analysis of a Spiking Neural Network Hardware Accelerator. - Theofilos Spyrou; Sarah A. El-Sayed; Engin Afacan; Luis A. Camuñas-Mesa; Bernabé Linares-Barranco; Haralampos-G. Stratigopoulos (DATE, 2022)

Using ANNs to Predict Frequency Spectrum Occupancy in Cognitive-Radio Receivers. - Promise I. Okorie; Luis A. Camuñas-Mesa; José M. de la Rosa 001 (DCIS, 2022)

A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP. - Luis A. Camuñas-Mesa; Elisa Vianello; Carlo Reita; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Study of foveation mechanisms in Dynamic Vision Sensors. - Isabel Ortíz-Ramírez; Luis A. Camuñas-Mesa; Bernabé Linares-Barranco; Teresa Serrano-Gotarredona (DCIS, 2023)

A multi-core memristor chip for Stochastic Binary STDP. - Ivan Diez-de-los-Rios; Luis A. Camuñas-Mesa; Elisa Vianello; Carlo Reita; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2023)

Combining Software-Defined Radio Learning Modules and Neural Networks for Teaching Communication Systems Courses. - Luis A. Camuñas-Mesa; José M. de la Rosa 001 (Inf., 2023)

Compact Functional Testing for Neuromorphic Computing Circuits. - Sarah A. El-Sayed; Theofilos Spyrou; Luis A. Camuñas-Mesa; Haralampos-G. Stratigopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems. - Promise I. Enwere; Encarnación Cervantes-Requena; Luis A. Camuñas-Mesa; José M. de la Rosa 001 (Integr., 2023)

Mismatch calibration strategy for query-driven AER read-out in a memristor-CMOS neuromorphic chip. - Luis A. Camuñas-Mesa; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2024)

A Fully Digital Relaxation-Aware Analog Programming Technique for HfOx RRAM Arrays. - Hamid Reza Erfani Jazi; Luis A. Camuñas-Mesa; Elisa Vianello; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

New self-calibration algorithm for programmable multi-core memristor-CMOS chip for neuromorphic computing. - Iván Díez de los Ríos; Luis A. Camuñas-Mesa; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2025)