A microprogram-based hardware implementation of the Leaky Bucket algorithm. - Luis A. Merayo; Juan I. Solana; Luisa Mola Morales (Microprocess. Microprogramming, 1991)

Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC. - Pierre Plaza; Juan Carlos Diaz; Fermín Calvo; Luis A. Merayo; Maurizio Zamboni; Pietro Scarfone; Marco Barbini (ED&TC, 1995)

A 2.5 Gb/s ATM switch chip set. - Pierre Plaza; Luis A. Merayo; Juan Carlos Diaz; José Luis Conesa (IEEE Trans. Very Large Scale Integr. Syst., 1996)

On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC. - Jacobo Riesco; Juan Carlos Diaz; Luis A. Merayo; José Luis Conesa; Carlos Santos; Eduardo Juárez Martínez (ED&TC, 1997)